Verilog - how to negate an array?

Question

reg a[4:0];
reg inv_a[4:0];

assign inv_a = ~a; //This doesn't work.

When I tried modelsim with above statement, it throw: "Illegal operation on unpacked types"

Can someone please point out how to correctly negate an array in Verilog?

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Edit: Give more information, does this change any recommendation?

module router_main(
    input bustorouter_ready[4:0],
);

  wire inv_bustorouter_ready[4:0];

  assign inv_bustorouter_ready = ~bustorouter_ready; //Still doesn't work.

Answer 1

A one-line solution to invert an unpacked array achievable via bit streaming (refer to IEEE Std 1800-2012 & sect; 11.4.14 Streaming operators (pack/unpack) for full details)

logic a[4:0];
logic inv_a[4:0];

assign {<<{inv_a}} = ~{<<{a}}; // bit streaming

Bit streaming only works in SystemVerilog. If you are limited to only Verilog, then you must use a for-loop or generate-for-loop (see Tudor's answer).

Another thing to consider is if unpacked arrays are necessary. Packed arrays allow access the array as a whole. Verilog does not allow passing unpacked arrays through port connections, packed arrays are allowed. SystemVerilog supports both packed in unpacked arrays as ports.

reg [4:0] a;
reg [4:0] inv_a;

assign inv_a = ~a; // pack array

General it comes down to how you want to access the array. Use packed arrays if you want to be treated as one number; individual elements access is still allowed. Use unpacked if you only intend to access individual elements in the array. For more on packed vs unpacked, refer to these earlier answered questions:

• SystemVerilog packed array vs unpacked array memory footprint
• packed vs unpacked vectors in system verilog

Answer 2

Try using a for loop in a combinatorial process:

always_comb
  for (int i = 0; i <= 4; i++)
    inv_a[i] = ~a[i];

Since I guess you're doing design, you'll need to check if your synthesis tool supports this construct.

Alternatively you could use a generate:

genvar i;
for (i = 0; i <= 4; i++)
  always_comb
    inv_a[i] = ~a[i];

Answer 3

Change your reg for a wire, as assign needs that:

reg [4:0] a;
wire [4:0] inv_a;

assign inv_a = ~a; //This should work.

Alternatively, you can keep inv_a as reg if you use an always block:

reg [4:0] a;
reg [4:0] inv_a;

always @*
  inv_a = ~a; //This should work.

reg a[4:0] seems to no be the same as reg [4:0] a;

reg a[4:0] is the same as reg [0:0] a[4:0] : an array of 5 registers of 1 bit each.

reg [4:0] a is a 5 bit register.

Reduction operators, as well as the unary inverter operator (this is bit-wise) operate only on a single vector (register). Your first declaration declared 5 vectors.

Answer 4

You can only perform logical operations on packed arrays(bit-vectors). The only operations allowed on unpacked arrays as a whole are copy and compare.

If you must do this in one line, you can cast the unpacked array to a packed array and back.

typedef logic  ua5[5];
typedef logic bit [4:0] pa5;
ua5 a; // same as reg a[4:0]
ua5 inv_a;

assign inv_a = ua5'(pa'(~a));

Otherwise, I would recommend a foreach loop

always_comb foreach (a[i]) inv_a[i] = ~a;

Answer 5

You can xor it with an array of ones:

assign inv_a = a ^ {WIDTH{1'b1}};

Answer 6

You can do inversion by using logical operations on packed array.

assign inverted_a = ((a)^(4'b1111));
X (XOR) 1 = ~X 

Then you can edit the binary number into the width of your input or register like 7'b11111111 or 3'b111.