Disambiguation
There is a strong difference between a multi-core based mode of operations, arranged in a "concurrent" manner and a parallel mode processing.
On Parallella board, if speaking about Zynq
-- a dual-core ARM Cortex-A9 CPU / Xilinx 7-series on chip FPGA -- for that you can get user
+ sys
values from on-board linux. Not the same for the Epiphany MPPA
( Massive Parallel Processor Array ) hardware device or additional parallelisable FPGA
-hardware loadable soft-CPU-cores.
Also note, that on a truly parallel system, the word "slower" or "slowest" core, loses its meaning as all processors start and finish in a parallel manner, for details kindly see the PAR
syntax constructor in occam-pi
( even at a cost of waiting for a divergent alternative path of processing, so as they all finish in parallel ).
How to?
One may include some signalling data to store during MPPA code-execution a clock counter value / later retrieved from Linux/ARM-side and use these telemetry-records data to evaluate ex-post the code-execution timing pre-recorded "inside-MPPA".
Doing the same in-real-time might be possible for in-vivo Tracing / State-Diagnostics / Inspect-Analyse-Tool but would require a lot of system specific engineering efforts for such a Real-Time-SysMONITOR.
However this is doable. Similar approach was used for visual inspection of state-transitions in FSA-design / validation.
A good explanation of conceptual and performance difference between a PARALLEL
, SERIAL
and CONCURRENT
mode of code-execution.