3

I’m kind of stuck on two problems. I will include the relevant details of the problem and any guidance would be appreciated. Please give explanations if you can.

Suppose you have the following statistics for a Processor with several different choices for memory hierarchy. 

Base CPI = 1.5 
Processor Speed = 2 GHZ
Main Memory Access Time = 100ns
L1 miss rate per instruction = 7%
L2 direct mapped access = 12 cycles 
Global miss rate with L2 direct mapped = 3.5%
L2 8-way set associative access = 28 cycles 
Global miss rate with L2 8-way set associative access = 1.5%

Note: A global miss rate is the percentage of references that miss in all levels of cache (and therefore must access Main memory)

  1. Calculate the Total CPI if L2 cache is available and is direct mapped.

  2. Calculate the Total CPI if L2 is available and is 8-way set associative.

Peter Cordes
  • 328,167
  • 45
  • 605
  • 847
Ockham
  • 455
  • 1
  • 6
  • 16
  • Related: real world CPU-design reasons why we use multi-level caches at all: [Why is the size of L1 cache smaller than that of the L2 cache in most of the processors?](https://stackoverflow.com/a/38549736) – Peter Cordes Jan 06 '21 at 04:28

2 Answers2

7

I now understand the problem so I thought I’d explained it on here to improve the forum with more information.

First,

Total CPI = Base CPI + Memory-Stall Cycles per Instruction

Memory-Stall Cycles per Instruction = Miss Penalty (in cycles) x Miss Rate

The first order of business is to figure out the miss penalty if there was not a second cache. This is easily determined by the following calculation:

Main Memory Access Time/ (1/Processor Speed) = (100) / (.5) = 200 cycles

Note: Main Memory Access Time is in ns, and the inverse of Processor Speed will be in ns/cycles, so by dividing the two we get the number of cycles. We are doing this calculation because it takes a certain amount of time to go all the way to main memory (100ns) and the processor speed determines how fast we can go (2GHz) and by changing clock speed to clock rate by inversion we can calculate the number of cycles required to go to main memory (miss penalty).

Because the problem involves two caches, when there is a miss in L1 there will be an attempt to retrieve the information from L2 and then if the information is still not found it will access main memory, so the flow looks something like this.

Access L1 -----> Access L2 -----> Access Main Memory

(it’s implied that if there is a “hit” we will not need to continue the flow)

The problem tells us that L2 direct mapped access takes = 12 cycles

So the calculation will look as follow:

Total CPI = 1.5 + (0.07 x 12) + (0.035 x 200) = 9.34 CPI

Because you miss 7% of the time you will need to access L2 and that takes 12 cycles so you multiply the two. Then if it’s still not found we must access main memory which takes 200 cycles and the global miss rate is 3.5%

Total CPI = 1.5 + (0.07 x 28) + (0.015 x 200) = 6.46

The second calculation is done in a similar fashion

Ockham
  • 455
  • 1
  • 6
  • 16
1

Part of the answering the first question is based off of interpretation. I thought it meant that we are supposed to calculate the CPI if there was only one cache level. That changes things a lot....

  1. Only a L1 cache in the system

    Miss penalty = 100ns/(1/2GHz) = 200 cycles First-level Cache CPI = 1.5 + (0.07 * 200) = 15.5

  2. L2 direct-mapped cache

    L1 miss, L2 hit penalty = 12 cycles Both miss penalty = 12 + 200 = 212 cycles Total CPI = 1.5 + (0.07 * 12) + (0.035 * 212) = 9.76

  3. L2 eight-way set associative cache

    L1 miss, L2 hit penalty = 28 cycles Both miss penalty = 28 + 200 = 228 cycles Total CPI = 1.5 + (0.07 * 28) + (0.015 * 228) = 6.88

And, just to note, this is problem 5.7.4 from the 5th edition of Computer Organization and Design by Patterson and Hennessy

ahogen
  • 759
  • 8
  • 20