1

I am unable to understand the usefulness of LOOPNE. Even if LOOPNE was not there and only LOOP was there, it would have done the same thing here. Please help me out.

MOV CX, 80
MOV AH,1
INT 21H
CMP AL, ' '
LOOPNE BACK

2 Answers2

4

CMP is more or less a SUB instruction without changing the value, which means that it sets flags such as ZF (the zero flag).

LOOPNE has 2 conditions to loop: cx > 0 and ZF = 0

LOOP has 1 condition to loop: cx > 0

So, a normal LOOP would go through all characters, whereas LOOPNE will go through all characters, or until a space is encountered. Whichever comes first

Andrew Brock
  • 1,374
  • 8
  • 13
  • What would zero flag have to do in this example? –  May 01 '12 at 19:25
  • zero flag is set when the result of the `CMP` (subtraction) is 0. This means that the zero flag is set to 1 when `AL` is a space character, which breaks the loop – Andrew Brock May 01 '12 at 19:27
  • LOOPNE = LOOP Not Equal. As the name suggests, loops while the most recent comparison was not equal – Andrew Brock May 01 '12 at 19:28
1

LOOPNE loops when a comparison fails, and when there is a remaining nonzero iteration count (after decrementing it). This is arguably very convenient for finding an element in a linear list of known length.

There is little use for it in modern x86 CPUs.

The LOOPNE instruction is likely implemented internally in the CPU by microinstructions and thus effectively equivalent to JNE/DEC CX/JNE. Because the CPU designers invest vast amounts of effort to optimize compare/branch/register arithmetic, the equivalent instruction sequence is likely, on a highly pipelined CPU, to execute virtually just as fast. It may actually execute slower; you'll only know by timing it. And the fact that you are confused about what it does makes it a source of coding errors.

I presently code the equivalent instruction sequence, because I got bit by a misunderstanding once. I'm not confused about CMP and JNE.

Ira Baxter
  • 93,541
  • 22
  • 172
  • 341
  • Instructions like "loop" or "loopne" can be funny when it comes to pipelined machines. Sometimes silicon venders will try to optimize them so that they're faster than an equivalent instruction sequence. Sometimes a vendor may conclude that there's no simple way to make them faster than the equivalent instruction sequence, so they'll advice programmers not to use them, and handle their appearance in legacy code with a microcoded "weird instruction processing" unit which may execute them operate more slowly than the main CPU could process the equivalent instruction sequence. – supercat May 01 '12 at 19:49
  • My point is you can bet on the vendor to optimize typical instruction sequences. You can't count on them to optimize "CISC" type instructions, so unless you are going to use a specific CPU for which such an optimization guarantee is made, its a bad bet the they are "fast". (This of course makes CISC instructions less used, which makes vendors want to optimize them less, ... eventually these instructions are likely to simply deprecated then removed from the instruction set, unless there's a killer application that uses them.) – Ira Baxter May 01 '12 at 19:58