It is possible.
In addition to dave and other posters' answers, I wrote a python script that will produce the code trickery that will run on both x86 and ARM which will take different paths depending on which is booting.
I'm not familiar with x86 so forgive me if this doesn't work.
import sys
import struct
import math
armClobberReg = 0
armShift = 31
if (armClobberReg>15):
sys.stderr.write("Error! ARM clobber register is invalid\n")
sys.exit(-1)
if (armClobberReg == 15):
sys.stderr.write("Warning: r15 will be clobbered on ARM\n")
if (armShift & 1 != 1 or armShift > 31):
sys.stderr.write("Warning! ARM shift is invalid. Using 31 instead\n")
armShift = 31
jmpOffset = (armClobberReg<<4)|(armShift>>1)
jmpAndEqNopInstruction = struct.pack("<BBBBI",0xE9, jmpOffset,0,0,0xE1A00000)
armNoOp = struct.pack("<I",0xE1A00000)
x86NoOp = struct.pack("c","\x90")
asmOut = jmpAndEqNopInstruction
asmArmTxtOut = "{0:08x}: andeq r{1}, r0, r9, ror #{2}\n".format(0, armClobberReg, armShift)
asmArmTxtOut+= "{0:08x}: nop\n".format(4)
asmx86TxtOut = "{0:08x}: jmp {1:x}\n".format(0, jmpOffset)
asmx86TxtOut+= " ... (ARM instructions)\n"
i = math.floor((jmpOffset + 5)/4) - 2
armPc = 8
while i>0:
asmOut += armNoOp
asmArmTxtOut+= "{0:08x}: nop <replace with your arm instructions>\n".format(armPc)
armPc+=4
i-=1
asmOut = asmOut.ljust(jmpOffset + 5, chr(0xff))
asmOut += x86NoOp
asmx86TxtOut += "{0:08x}: nop <replace with your x86 instructions>\n".format(jmpOffset + 5)
asmArmTxtOut += " ... (x86 instructions)\n"
sys.stderr.write("x86 disassembly: \n"+asmx86TxtOut+"\n")
sys.stderr.write("ARM disassembly: \n"+asmArmTxtOut+"\n")
sys.stderr.write("ARM code length limited to {0} instructions\n".format(int(math.floor((jmpOffset + 5)/4) - 2)))
sys.stdout.write(asmOut)
sys.stderr.write("Wrote opcodes to stdout\n\n")
On ARM, the first and second instruction is interpreted as an andeq
and nop
instruction while on x86, it is interpreted as a jmp
instruction.
ARM disassembly:

x86 disassembly:

You can append your own opcodes in it that will branch to the appropriate kernel.