5

I have the following GNU makefile:

.PHONY a b c d

a: b c
b: d
c: d
d:
    echo HI

I would like the target 'd' to be run twice -- since it is specified as a dependency by both b & c. Unfortunately, the target 'd' will be executed only once. The output of running make will simply be 'HI', instead of 'HI HI'.

How can I fix this?

Thanks!

To Clarify, the goal is something like this:

subdirs =  a b c

build: x y

x: target=build
x: $(subdirs)

y: target=prepare
y: $(subdirs)

$(subdirs):
    $(make) -f $@/makefile $(target)

2 Answers2

3
build: x y

x: target=build
y: target=prepare

x y: 
    echo hi $(target) $@
    touch $@

See also GNU Makefile rule generating a few targets from a single source file as it is an answer to a problem that is the opposite of this one.

Community
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ctrl-alt-delor
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1

Are you trying to do something like this:

.PHONY: a b c

define print-hi
@echo HI
endef

a: b c
b:
    $(print-hi)
c:
    $(print-hi)
Karl Voigtland
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  • Not quite. More something like this: subdirs = a b c build: x y x: target=build x: $(subdirs) y: target=prepare z: $(subdirs) $(subdirs): $(make) -f $@/makefile $(target) –  Aug 02 '09 at 03:07