Makefile export .o file to a different path than .cpp

Question

So my task is simple, I have created the makefile (New with makefiles) and I want to keep my .o files in a different folder to have a cleaner directory and allow the usage of .o files by others.

I searched and found many solution pointing to using -o $< $@

However, it is giving me that g++: cannot specify -o with -c or -S with multiple files

This is what I want to do:

$(OBJECT_PATH)/file1.o: $(SOURCE_PATH)/file2.cpp $(SOURCE_PATH)/file1.cpp
        $(CC) $(CFLAGS) $(SOURCE_PATH)/file2.cpp $(SOURCE_PATH)/file1.cpp -o $@

file1.cpp has #include "file1.h", so from what I read I should include file1.cpp in the dependencies. However, now I can't export to a different directory.

Is there a solution? Or do I have the concept wrong?

Why do you have a *single* `file1.o` depending upon *two* source files `file2.cpp` and `file1.cpp` ? This is unusual.... Usually `file1.o` depends upon `file1.cpp` and other header files, and `file2.o` depends upon `file2.cpp` and other header files.... and the entire executable is made with `file1.o` and `file2.o` etc.. linked with some libraries. — Basile Starynkevitch, Nov 01 '12 at 11:31

Basile Starynkevitch · Accepted Answer · 2012-11-01T11:41:02.143

Use make -d or even better remake -x to understand what commands are invoked.

Run also make -p to understand what builtin rules are used.

We cannot help you more, because we have no idea if you redefined CFLAGS.

And C++ compilation should better be done with g++ that is CXX and CXXFLAGS, e.g. with (I am extracting this from my make -p output)

LINK.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(LDFLAGS) $(TARGET_ARCH)
COMPILE.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
CXX = g++
%.o: %.cc
      $(COMPILE.cc) $(OUTPUT_OPTION) $<

I strongly suggest to have CXXFLAGS= -Wall -g at least during the development phase. Learn also to use gdb and valgrind.

You could have the following in your Makefile

 CXXFLAGS= -g -Wall
 SOURCES=f1.cc f2.cc
 SOURCE_PATH=yoursourcedir/
 OBJECT_PATH=yourobjectdir/
 SRCFILES=$(patsubst %.cc,$(SOURCE_PATH)/%.cc,$(SOURCES))
 OBJFILES=$(patsubst %.cc,$(OBJECT_PATH)/%.o,$(SOURCES))
 PROGFILE=$(OBJECT_PATH)
 .PHONY: all clean
 all: $(PROGFILE)
 $(PROGFILE): $(OBJFILES)
         $(LINK.cc) $^ $(LOADLIBES) $(LDLIBS) -o $@
 $(OBJECT_PATH)/%.o: $(SOURCE_PATH)/%.cc
         $(COMPILE.cc)  $(OUTPUT_OPTION) $<
 clean:
         $(RM) $(OBJECT_PATH)/*.o $(PROGFILE)

it is failing when linking. Do you have any idea why? It is giving undefined reference to functions — Syntax_Error, Nov 01 '12 at 23:42
Some object files or libraries are missing at the linking step, or the order of the arguments to the linking command are incorrect. Can't help more till you don't explain what exactly is failing. — Basile Starynkevitch, Nov 01 '12 at 23:59
Oh I see. I wasn't aware the arguments have to be in order. Can you explain or provide a link on how to put the order. THanks — Syntax_Error, Nov 02 '12 at 00:02

score 1 · Answer 2 · answered Nov 01 '12 at 10:57

1

try

$(OBJECT_PATH)/file1.o: $(SOURCE_PATH)/file2.cpp $(SOURCE_PATH)/file1.cpp
    $(CC) $(CFLAGS) $^ -c $@

and check that CFLAGS doesn't include -o -c or -s flags

also read about implicit rules. it might help you to orginzie your makefile

answered Nov 01 '12 at 10:57

Jah

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Makefile export .o file to a different path than .cpp

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