I believe it is possible to use the value of an environment variable inside a make file.
Since I'm new to bash and make, had a tough time figuring out how.
I tried the following, but no success.
In Bash
TEST_VAR=1
export TEST_VAR
In make file
ifeq ($(TEST_VAR),1)
COMMON_OBJECTS += Test1.o
endif
But It doesn't compile Test1.cpp.
My make file contains only these lines and I am adding COMMON_OBJECTS to another variable defined in another file.
If I comment this ifeq condition Test1 is getting compiled. But I am looking for a way to do this conditionally.
What I am missing here?