fiq & irq handler -- arm

Question

I am new to arm & have some doubs related to IRQ & FIQ. Please try to clarify these.
How many number of FIQ & IRQ channel arm have ?
And what number of handlers can we write for each channel ?
Also if we can register multiple handler for single interrupt channel how arm comes to know which handler to run.

That's not an ARM specific question. ARM is just an architecture / instruction set and how many IRQ & FIQ channels are available and how they work will depend on the final chipset manufacturer. You need to specify either the part you are using or what your requirements are so someone may be able to suggest a particular chipset. AFAIK they all pretty much only have one FIQ but the number of general IRQ channels varies widely depending on the base core used and what peripherals are available. — PeterJ, Dec 08 '12 at 12:01
Means manufacturer can send any number of IRQ to ARM, but these will go as an input to arm core.. so how can manufacturer of chipset... send as many IRQ they want. Also how chiset manufacturer tells core which handler to execute if there are multiple registerd osn same IRQ ? ... I am using Rpi. — Allan, Dec 08 '12 at 12:33
The Rpi uses a Broadcom BCM2835 based on the ARM1176JZF-S core. The full datasheet for the part is not completely public but http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf should contain the info you need. — PeterJ, Dec 08 '12 at 12:38
Just another comment - a manufacturer can put 1000 peripherals on a single IRQ if they choose and have registers (of their choice) to determine which one fired the interrupt. There's not really any standard in that regard which is why it's chipset specific. — PeterJ, Dec 08 '12 at 12:46
@ peter -- if an interrupt occurs now my interrupt controller knows who fired the interrupt & what type of interrupt it was(suppose IRQ). So it sends IRQ request to the ARM core. But how arm core will come to know where does the address of interupt handler starts will interrupt controller tell this to the ARM core ...????? — Allan, Dec 09 '12 at 05:46
The ARM core always jumps to address 0x00000018 (or 0xFFFF0018 if high vectors are enabled) when the IRQ line is asserted (and IRQs are enabled). — tangrs, Dec 09 '12 at 06:10
@user1871965 tangrs is right with the answer above, the address for each IRQ vector is fixed. The ARM core as such doesn't need to know where the interrupt came from, it just fires the code at that vector. Then it's up to your code to work out where it came from for a shared interrupt, which is normally via registers as defined by the particular chip. — PeterJ, Dec 09 '12 at 06:22
@peter tangrs ;-- means we have to write a common handler & put address of handler at -- 0xFFFF0018 . Now inside this handler check which is the right source for interrupt & execute interupt subhandler. Am i right ... ? But what if out of 30 shared interrupts on IRQ 2 occurs simultaneously & there bits are set in Interupt status register of interrupt controller.. Then how to make decision which interrupt to execute .. ? — Allan, Dec 09 '12 at 06:34
Yes you have to read the registers and determine yourself what handlers to call, presumably most important first. Looking at the BCM2835 datasheet I posted above it does have details of how all the interrupts are mapped and how you poll them. Right from the datasheet "It is up to the ARM software to device a strategy" (sic). You mentioned a Raspberry Pi, you realise none of this stuff can be done from Linux user code and you're going to either need to write your own kernel drivers or bootstrap from scratch with no operating system? — PeterJ, Dec 09 '12 at 07:02
@peter yes .. actually i started with device driver for arm ... there i saw for each handler mention --- __attribute__((interrupt( irq ))) ---- then only this thread start --- I am confused how this attribute will place a call to our driver routine ..?? Means some startup code will be provided by the GCC compiler for the IRQ handler & compiler will place call to our routine in that startup code for interrupt handler ..... Am i right ...? — Allan, Dec 09 '12 at 08:20
@user1871965 Now you have a better idea of what's involved you might be better starting a new question with more specifics on what you're trying to do exactly, and mention Rpi / BCM2835 / ARM1176JZF-S. The GCC compiler doesn't supply startup code and booting one from scratch is fairly complex. Also mention in the new question if you are using Linux or are just trying to write all the startup and interrupt code from scratch. — PeterJ, Dec 09 '12 at 08:38

marko · Accepted Answer · 2012-12-08T21:31:51.867

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The distinction between IRQ and FIQ goes right the way back to early days of ARM when it was designed by Acorn. It was always the case that the IRQ line was attached to an interrupt controller that multiplexed a large number of interrupt sources together. This is precisely what happens in all modern ARMs

The rationale behind the FIQ was to provide an extremely low latency response with maximum priority (it can safely pre-empt the IRQ handler). The comparatively large number of shadow registers facilitate writing handlers that store the handler's state in CPU registers and not hitting the stack.

The shadow registers are almost of the opposite set to those commonly used by APCS for function call, so writing handlers in C, would cause a push and eventual pop of up to 8 non-shadowed registers. Having any kind of interrupt demultiplexing wipes out any performance advantage that FIQ might have given.

All of this means that there is only really any benefit in using FIQ for very specialised applications where really hard-real time interrupt response is required for one interrupting device, and you're willing to write your handler in assembler. You'll also be left with working out how to synchronise with the rest of the system - some of which would rely on disabling IRQ to keep data synchronised.

edited Dec 08 '12 at 21:31

answered Dec 08 '12 at 19:49

marko

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@ Marko -- if an interrupt occurs now my interrupt controller knows who fired the interrupt & what type of interrupt it was(suppose IRQ). So it sends IRQ request to the ARM core. But how arm core will come to know where does the address of interupt handler starts will interrupt controller tell this to the ARM core ...????? – Allan Dec 09 '12 at 05:46
1

Usually the *interrupt controller* is a hardware unit that multiplexes many interrupt lines together, generating single line to the CPU. When an interrupt occurs, the controller asserts the IRQ line. The CPU stops executing and jumps through the IRQ vector (location varies) to the interrupt handler. The interrupt handlers reads a register on interrupt controller to determine the interrupt line and, invokes the correct interrupt handler and then clears the interrupt - allowing another to occur. – marko Dec 09 '12 at 12:36
Err, since this is the accepted answer; it seems the OP wanted to ask [this question](http://stackoverflow.com/questions/973933/what-is-the-difference-between-fiq-and-irq-interrupt-system), which might be helpful to others. This answer, manav's and mine (in the other question) all say mostly the same thing. – artless noise May 22 '14 at 21:46

score 3 · Answer 2 · answered Dec 08 '12 at 18:10

traditionally the arm has one interrupt line which you can send to one of two handlers FIQ or IRQ. FIQ has a larger bank of FIQ mode only registers so you have fewer that you need to store on the stack. From there you read the vendor specific registers if any to determine the source of the interrupt and then branch into separate handlers.

More recently there have bend arm architectures with many interrupts 128, 256 each with a separate handler. So generically asking about arm is not as varied but about like asking something generic about x86.

All of this information is easily available in the ARM architectural reference manuals for the different architectures and the pinouts to the core (what the vendor builds its chip around) is documented in the technical reference manuals for the various cores (also very easy to obtain). infocenter.arm.com has the architecture and technical reference manuals as well as amba/axi (the data bus that the vendor connects to). Your question is completely answered in those documents.

irq and fiq might be two separate inputs to the core but the implementations I am used are such that you as a programmer can choose irq or fiq you are not locked into one or the other. — old_timer, Dec 08 '12 at 18:11

score 1 · Answer 3 · answered May 28 '15 at 15:54

The ARM processor directly supports only ONE IRQ and ONE FIQ. ARM supports multiple interrupts through a peripheral called Interrupt Controller. ARM standard interrupt controllers are called GIC (Generic Interrupt Controller).

The GIC has a number of inputs for peripherals to connect their interrupt lines and two output lines that connect to IRQ and FIQ. Basically it acts as a MUX. A GIC driver will setup configurations such as interrupt priority, type (IRQ/FIQ), masking etc.

In traditional ARM systems there is one entry each for IRQ and FIQ in the Exception Vectors. Depending on which line the interrupt fired, IRQ or FIQ handler is called. The interrupt handler queries the GIC (GIC CPU interface registers, to be specific) to get the interrupt number. Based on this interrupt number, corresponding device handler is invoked.

Number of interrupts depends on the specific GIC implementation. So you would have to check the manual for the interrupt controller in your system to get those specifics.

Note: The interrupt handling is slightly different depending on which specific ARM core you are coding for.

score 0 · Answer 4 · answered Feb 22 '16 at 20:14

Actually the question is a bit tricky. You must specify in the question to which architecture in ARM you work. ARM v7-A and ARM v7-R Architecture Reference Manual (ARM ARM) specifies one FIQ and one IRQ, as many already answered. But ARMv7-M (used in Cortex-M processors) integrates a interrupt controller in the processor, and thus offers one NMI (instead of FIQ) and up to 240 IRQ lines.

For more information: ARMv7 A and ARMv7-R Architecure reference manual: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html

ARMv7-M Architecture Reference Manual: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403e.b/index.html

As an example, Cortex M4 specs sheet: http://www.arm.com/products/processors/cortex-m/cortex-m4-processor.php

fiq & irq handler -- arm

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