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I am looking for L1 access latency and L2 access latency for SoCs made from ARM Cortex-A9 processors such as Nvidia Tegra 2 and Tegra 3 which have multiple ARM A9 processors.

I could find some information about the L1 and L2 size of those architectures, but I could not much information about the L1 and L2 access latency. The only reliable information I found is that "L2 cache latency is 2 cycles faster on Tegra 3 than 2, while L1 cache latencies haven't changed."

Here is mentioned that L2 on Tegra 2 has a latency of 25 cycles and here is mentioned that L1 has a latency of 4 cycles and L2 has a latency of 31 to 55 cycles. None of these references are fully reliable. I was hoping to find more info on Nvidia, TI, and Qualcomm websites and technical documents, but no success.

EDIT: information on similar SoCs like OMAP4460 and OMAP4470 would be great too.

artless noise
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aminfar
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  • May I ask why do you need this? – auselen Dec 17 '12 at 08:41
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    to do some cache performance comparison on SoCs that use ARM-A9 processors. The cache for A9 can be architected in different ways, so you'll end up systems with very different performance and energy consumption. I need to have these cache numbers so I could speculate A9 performance for some applications. – aminfar Dec 17 '12 at 20:52
  • L1 is tightly coupled with A9, L2 is generally L2C-310. What do you mean by architected in different ways? They have a few settings for ram latencies or they can have different sizes. Cache latencies in general is not trivial. See the titles under here http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246h/BABIECJB.html – auselen Dec 17 '12 at 23:24
  • I found some numbers on p. 28 [here](http://wenku.baidu.com/view/eae3f1fbfab069dc5022018b.htm) which compare UP vs MPCORE with and without L2C-310. That doc suggests L1 latency should be 1 cycle (I'm not sure); L2 numbers are marginally less than what you noted. But as auselen has noted, there are settings that affect L2. – Joe Kul Dec 20 '12 at 19:52
  • Did you find these infos? I need to know these (i.e. clean/dirty L1/L2 access latency) for A9 MPCore. Any advice? – JohnTortugo Aug 01 '14 at 19:54
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    @JohnTortugo Not much more info apart from the info that you can find on the links in this post. – aminfar Aug 04 '14 at 17:55

1 Answers1

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For an authoritative answer, you can try running lmbench (HowTo?) on the target of your choice.

A set of results for AM37x (variant of TI OMAP3 family) is available here for reference.

Also checkout this presentation that describes the latency and bandwidth of various caches configurations on an ARM Cortex A9 MP system.

TheCodeArtist
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