What do the makefile symbols $^ mean?

Question

makefile:

$(TARGET): $(OBJ)
    $(GCC) $(LDFLAGS) -o $@ $^

What $@ and $^ exactly do in make file?

score 4 · Answer 1 · answered Feb 11 '13 at 05:09

4

$^ is the set of dependent files used to build something else.

$@ is the name of the target to be built.

answered Feb 11 '13 at 05:09

aschepler

score 3 · Answer 2 · answered Feb 11 '13 at 05:10

3

$@ is the name of the target. This is quite useful when the target is a pattern rather than fixed.

$^ is the name of the prerequisite that caused the rule to execute.

answered Feb 11 '13 at 05:10

PQuinn

2 Answers2