I have a single makefile that runs a group of tests involving various files and writes the results to log files. Is it possible to write the makefile so that it will run the same set of shell commands after all other targets in the file have been processed, regardless of errors that occurred.
I know I could use a shell script that calls the makefile and then the shell commands, but I'm wondering if it's possible to do this from within the makefile itself, without using some phony target like make print
(for example).