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In an existing GNU Make build system, I'd like to see a tree of the makefile includes. How may I do this? Like Do you know tool building tree of include files in project\file? but for GNU Make rather than C and C++.

A related but slightly different capability I'd be interested in: being able to put $(info ...) statements in a makefile and have it print out a backtrace of includes for that info statement.

Community
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TheDude
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1 Answers1

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If you just want a list of included makefiles, a $(info Included files: ${MAKEFILE_LIST}) at the bottom of the main makefile fits the bill.

However, if you do want a tree, then you'll have to replace all include <file> with $(call include,<file>). The include function would be something like:

space :=
space +=
${space} := ${space}

stack := $(firstword ${MAKEFILE_LIST})

define includefunc
  stack := $(subst ${ },|,$(strip ${MAKEFILE_LIST} $1)) ${stack}
  $(info INCLUDES $(firstword ${stack}))
  include $1
  stack := $(wordlist 2,$(words ${stack}),${stack})
  MAKEFILE_LIST := $(subst |, ,${stack})
endef

include = $(eval $(value includefunc))

$(call include,1.mak)
$(call include,_1/1.mak)
$(call include,folder/Makefile)

.PHONY: all
all: ; echo $@ success
bobbogo
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    Use of spaces in variable names (`${space} := ${space}`) is not permitted in recent versions of GNU Make: http://lists.gnu.org/archive/html/help-make/2012-01/msg00052.html – Eldar Abusalimov Feb 28 '13 at 10:30
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    The way bobbogo has done it it will still work; from the GNU make NEWS file: Second, variable names can no longer contain whitespace, _unless you put the whitespace in a variable and use the variable_ – MadScientist Feb 28 '13 at 12:31