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I recently started off with a course on Computer Architecture from an online resource. I read from one of the books I picked up, that x86 processors have 32 address lines and can read in data 4 bytes at a time on the data bus. Now I understand that 32 address lines place a limit on the addressable memory to 4 billion unique addresses. What I'm having difficulty wrapping my head around is the fact that if the CPU can read in 4 bytes of data at each cycle, from each of those 4 billion unique addresses, why is the RAM on x86 systems limited to 4 GB. Shouldn't it instead be 16 GB (4 times 4 GB)? Could someone clear this up for me? Also when I talk about 32-bit or 64-bit microprocessors, does 32/64 refer to the number of address lines or the number of data lines on the CPU? (For my first question, I should probably mention that I'm assuming a system with no physical address extension.)

HungryTux
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    Because 4 bytes isn't the smallest addressable unit. – Mysticial Feb 27 '13 at 16:11
  • @Mysticial I didn't quite get your point. Could you please elaborate? – HungryTux Feb 27 '13 at 16:16
  • The processor needs to be able to address each individual byte. Therefore you don't get that "for free" factor of 4. – Mysticial Feb 27 '13 at 16:18
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    Ok so if I understand this right, even though the processor pulls in 4 bytes at each instruction cycle from the data bus, each of these 4 bytes belong to 4 different addresses in memory. Its just that they were all pulled in, in one go. Is that correct? – HungryTux Feb 27 '13 at 16:21
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    Here's a good SO answer http://stackoverflow.com/questions/2724449/different-between-word-addressable-and-byte-addressable – amdn Feb 27 '13 at 16:22
  • Not quite. You can load one byte at a time on x86. That's why they need to be individually addressable. – Mysticial Feb 27 '13 at 16:23
  • @amdn That clears up a lot of things. – HungryTux Feb 27 '13 at 16:27
  • @Mysticial Thanks, I figured that after I read the thread posted by amdn above. As for my second query, can I generalize the '32/64' to be the number of address lines on the CPU when talking about 32-bit or 64-bit microprocessors? – HungryTux Feb 27 '13 at 16:30
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    If you mean "address *bits*", then yeah. That's the convention. – Mysticial Feb 27 '13 at 16:33

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x86 microprocessors is a broad category of processors that has evolved over decades from the 8086 to today's 64-bit multi-core CPUs. One of the strengths of the x86 processors is that they are backward compatible, meaning that the latest processors in the family understand the instructions of the 8086 (they would have to run in a special mode called Real Mode). The 8086 had 16-bit registers and a 16-bit bus to memory and I/O, it was byte addressable meaning the address used by the program was that of an individual byte. The 8086 could load either 1 or 2 bytes (known as a word) from memory. Over time newer x86 processors added more bits to the address lines, and added virtual memory, and added larger words. So a 32-bit data item was called a double word and a 64-bit data item became known as a quad word and then SSE came along and we had 128-bit octaword or double quadword, here's a table of data sizes. The newer x86 processors can access data in any of those sizes, in fact the latest have AVX instructions which have 256-bit vector registers. Addressing memory, from the point of view of the program, is still done by giving the address of the byte at the lowest address.

You can read more about 64-bit computing here. Here's a good summary:

Without further qualification, a 64-bit computer architecture generally has integer and addressing registers that are 64 bits wide, allowing direct support for 64-bit data types and addresses. However, a CPU might have external data buses or address buses with different sizes from the registers, even larger (the 32-bit Pentium had a 64-bit data bus, for instance).

amdn
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