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I have written a makefile for my source code , and depends on the makfile input variable I include some dependable source files .

 ifeq($(var),mod1)
 src + = mod1.cpp 
 else ifeq ($(var),mod2)
 src + = mod2.cpp 
 else ifeq ($(var),mod3)
 src + = mod3.cpp 
 endif 

I compile this using $make var=mod1 . this works fine when I want to include a single variable . But I need to provide the option to include any combination of variable among mod1,mod2,mod3 .

Like $make mod1 mod2 or make mod3 mod1 etc

How to provide these kind of combination in the make file?

Synxis
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indra
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1 Answers1

2

You can pass multiple argument to make file as you want.

Make File (makefile)

all:
     echo $(NAME)
     echo $(AGE)
     echo $(TEL) 

In console

make NAME=your_name AGE=your_AGE TEL=your_tel -f makefile
Nayana Adassuriya
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  • I thought the same and posted almost the same answer, but deleted it, because it's not what the OP wants. @indra wants to avoid using `var_name=var_value` but use `var_value` directly. – Kiril Kirov Apr 01 '13 at 09:19
  • @KirilKirov: OP needs to use argument in random order. so in common sense, it is impossible to use without descriptor. – Nayana Adassuriya Apr 01 '13 at 09:24
  • This soln may help , is it possible to check whether user has mentioned in the make file argument ,, ? .. like I want to just check $make ENABLE_NAME ENABLE_AGE etc .. – indra Apr 01 '13 at 09:25