4

I've got this directory structure:

  • ./src contains the the .cpp and the .h of all the files I need
  • ./bin should contain the .o temporarily and the .bin permanently. Also, this folder should be deleted when calling make clean.
  • ./ contains the Makefile

This is my current Makefile:

CFLAGS = -Wall -pedantic -g
CC = g++
EXEC = flrfile
SRC_DIR = src
BIN_DIR = bin
OBJ = FixedLengthFieldsRecord.o FixedLengthRecordFile.o main.o

all: flrfile

../$(BIN_DIR)/%.o: $(SRC_DIR)%.cpp $(SRC_DIR)%.h
    $(CC) $(CFLAGS) -c $(SRC_DIR)%.cpp -o $@

$(EXEC): $(OBJ)
    @mkdir -p bin
    $(CC) $(CFLAGS) $(BIN_DIR)/$(OBJ) -o $(BIN_DIR)/$(EXEC)

.PHONY : clean

clean:
    -rm -rf $(BIN_DIR)

When I run make, I get this error:

make: *** No rule to make target `FixedLengthFieldsRecord.o', needed by `flrfile'.  Stop.

Why is this?

PS: Also, how could I make the OBJ = FixedLengthFieldsRecord.o FixedLengthRecordFile.o main.o more generic? I don't want to write all the .o...

Maria Ines Parnisari
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1 Answers1

3

It's because you don't have a rule for something.o, you have a rule for ../bin/something.o.

If you change your OBJ declaration to

OBJ = ../$(BIN_DIR)/FixedLengthFieldsRecord.o ../$(BIN_DIR)/FixedLengthRecordFile.o ../$(BIN_DIR)/main.o

It should work.

You could get objects from source dir using wildcards

SOURCES := $(wildcard $(SRC_DIR)/*.cpp)
OBJ := $(patsubst $(SRC_DIR)/%,%,$(SOURCES))
OBJ := $(patsubst %.cpp,%.o,$(OBJ))
OBJ := $(addprefix ../$(BIN_DIR)/,$(OBJ))

What this does is that first it get a list of cpp files from $(SRC_DIR), removes the path, then replaces all cpp suffixes for o and lastly add `../$(BIN_DIR)/' in front of each item.

Akobold
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