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I have two low-level question about how memory interleaving across channels works on Sandy Bridge processors. I've poured through technical documents from Intel, and I still cannot find the answers. Can you help?

Multi-channel memory controllers in modern CPUs stripe data across the memory channels. This allows reads and writes to be carried out in parallel, thus increasing performance.

Question #1: What is the chunck size Sandy Bridge uses for interleaving? I've found some information that suggests that it is the cache-line size. On the other hand, others have suggested that it is configurable (at least in older Intel architectures). Which is it? Can you point to an Intel document?

Some CPUs allow interleaving to be disabled. This is confirmed by BIOS settings of some high-end systems such as HP's ProLiant and Fujitsu's Primergy. The closest documentation from Intel that I can find on this is section 4.4.4.3 in this E5 Product Family Data Sheet. I have gone as far contacting HP about how their ProLiants work when interleaving is disabled, but even on a conference call, they were unable to answer my question.

Question #2: How is memory mapped across the channels when interleaving is disabled? Presumably, it is different from spare or mirror mode configurations.

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Glenn
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  • BIOS Documents: [HP ProLiant](http://h20000.www2.hp.com/bc/docs/support/SupportManual/c03293145/c03293145.pdf) (page 25), [Fujitsu Primergy](http://globalsp.ts.fujitsu.com/dmsp/Publications/public/wp-sandy-bridge-ep-memory-performance-ww-en.pdf) – Glenn Apr 05 '13 at 14:20
  • I don't have the answer. But I think the page 48 of lecture 5 on http://class2go.stanford.edu/EE282/Spring2013# would help – Zhe Yang Aug 11 '13 at 12:23
  • Possibly related forum thread, was posted in a link-only answer which is now deleted: http://www.overclockers.com/forums/showthread.php/763193-64-byte-cache-line-size-for-Haswell-E-Sandybridge-E-and-4-channel-memory. – Peter Cordes Oct 27 '17 at 06:57

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