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Ok, as far as I understand, in polling mode I need to continually check UART registers to both receive and send characters. I have that working, and next step is dealing with FIFO. I enabled it and didn't chance the read / write operations and everything still works the way it used to.

For now I am not using interrupts.

Is there anything I need to do in order to specifically take advantage of FIFO mode instead of just probing the TX and RX registers?

It seems to me that in polling, FIFO or no FIFO makes little difference, at least when baud rate is 1200.

Aleister
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2 Answers2

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Polling FIFO vs polling non-FIFO ideas:

1) For both input & output, you likely have an IsXmitFull() and IsRcvNotEmpty() routines. Exercise care in using the negation of these functions.

// Say you want to test is all the data is transmitted
if (!IsXmitFull()) {  // This is OK in non-FIFO poling, but not in FIFO polling.
// You need a new `ISXmitEmpty()` function.  This function not only tests if the shift register is empty but also the FIFO.

2) If you are doing RS-485 (shared transmit/receive lines), you need to watch for the greater latency the FIFO causes before you change the direction of the bus.

3) When you receive an error, your corrective action (resetting the PIC's UART?) tends to affect more data - like losing the offend byte and the next 1, 2 or 3.

4) If you go into low-power/clock speed mode, observe the latency of you FIFO. (Insure all data is out before slowing your clock.)

5) If you employ XON/XOFF hand shaking, again note the FIFO increase latency issues.

6) May some other arcane issues, but TTFN.

chux - Reinstate Monica
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Correct, for polling, FIFO or non-FIFO makes no difference. Bit 5 or LSR register indicates THR register is empty or not. In FIFO mode, this bit just tells whether the FIFO is empty or not (So does Bit 6 of LSR, but this also indicates whether tx transmission is complete or not). By polling, it is not possible to know what is the current depth of the tx FIFO.

In some UARTs, there is a special THRE (Transmit Holding Register Empty) interrupt mode, which if enabled, switches the functionality of LSR[5] to indicate whether tx FIFO is full or not. This is helpful, since we can continuously write to the tx FIFO until this bit becomes 1.

For data reception, whether or not in FIFO mode, LSR[0] indicates whether data is available for read (irrespective or whether it comes from FIFO or RBR register) or not.

appusajeev
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