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I would like to design and implement a bare metal, OS-like simple and safe scheduler.

The mechanism should handle IRQ context (USB and SDH), and 3-4 main subroutines two of them manipulate both USB and SDH controllers and all have some CPU usage.

What is the best and most efficient direction to go with for ARM cortex A12 single core, in order to implement a safe scheduling mechanism runs all the subroutines (all on privileged mode) and can handle the IRQ context?

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0x90
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  • Have you written any code? Do you have a more specific question? There are plenty of free real-time executives out there that you could look at for examples. – Carl Norum Sep 20 '13 at 15:45
  • I am trying to figure out the correct design and then try to implement it by myself, I am not sure I took all the right considerations yet. I have all the subroutines and irq handler implemented, long code, but I want to wrap them and scheduling them in the right way. thanks – 0x90 Sep 20 '13 at 15:47
  • Your question will probably be closed as too broad or off-topic unless you make it more specific. – Carl Norum Sep 20 '13 at 15:48
  • I believe it is a design question and self contained if you think I should elaborate and add more details please let me know. – 0x90 Sep 20 '13 at 15:50
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    It definitely requires an *opinion*. A clear design criteria is pre-emptive vs non-preemptive. As well, I would assume no MMU? If it is non-preemptive (or co-operative), you don't need to save any registers on a context switch and code your ISR in assembler; that makes the scheduler very efficient. I think **best** is the over-loaded portion of your question you need to address. – artless noise Sep 20 '13 at 17:54
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    Maybe [Simon Tatham coroutines](http://www.chiark.greenend.org.uk/~sgtatham/coroutines.html) are interesting to you. See also [Coroutine at wikipedia](http://en.wikipedia.org/wiki/Coroutine) or Donald Knuth's books if you have them. – artless noise Sep 20 '13 at 18:52
  • @artlessnoise thanks for the awesome link by Simon, but I don't understand how can courtines can exploited to improve I/O performance. – 0x90 Sep 21 '13 at 07:46
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    Basically, you have one *co-routine thread* that processes **USB**. When there is no more data to process, it *yeilds* and either the **SDH** user thread runs or a higher layer **USB** routine. Your *ISRs* would *feed* the co-routines. I guess the *routines* are processing different layers. When you have a big enough chunk, you can proceed to the next layer. This helps *cache locality* and you should get better *I/O* performance, if structured correctly. – artless noise Sep 21 '13 at 19:55
  • @artlessnoise I read data from USB from PC and write it to flash, meanwhile I do some CPU work. please try to format all your comments to an answer. thanks – 0x90 Sep 21 '13 at 21:18
  • That may help [Super Simple Tasker (SST)](http://www.embedded.com/design/prototyping-and-development/4025691/Build-a-Super-Simple-Tasker) – 0x90 Sep 22 '13 at 01:20

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If cooperative threading is enough for you, you could try Lua language, it has native support for coroutines and it interfaces easily with C code. There is also a port for embedded processors: see eLua.

LorenzoDonati4Ukraine-OnStrike
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