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I want to initialize on a bare metal cortex A-15 the NEON cp. After following ARM's directives I wrote this sequence at the end of my platform init sequence:

MOV r0, #0x00F00000
MRC p15, 0, r0, c1, c1, 2
ORR r0, r0, #0x0C00 
BIC r0, r0, #0xC000 
MCR p15, 0, r0, c1, c1, 2
ISB
MRC p15, 4, r0, c1, c1, 2
BIC r0, r0,  #0x0C00
BIC r0, r0, #(3<<14)
MCR p15, 4, r0, c1, c1, 2
ISB
MOV r3, #0x40000000
VMSR FPEXC, r3

I get this error:

Error: operand 0 must be FPSCR -- `vmsr FPEXC,r3'

I am using arm-eabi-as --version:

GNU assembler (GNU Binutils) 2.21
Copyright 2010 Free Software Foundation, Inc.
This program is free software; you may redistribute it under the terms of
the GNU General Public License version 3 or later.
This program has absolutely no warranty.
This assembler was configured for a target of `arm-eabi'.

If I change FPEXC to FPSCR the program compiles and the running raise unhandler exception:

MRC p15, 4, r0, c1, c1, 2
0x90
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  • @artlessnoise any idea why `MRC p15, 4, r0, c1, c1, 2` raises an exception and changes the mode to `Undefined` in [CPSR register](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/I27695.html)? I am running the above assembly code as `Supervisor`. – 0x90 Oct 07 '13 at 19:09
  • @artlessnoise, that is what [ARM claims](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CDEDBHDD.html) – 0x90 Oct 07 '13 at 20:07
  • I think you need `MRC p15, 0, r0, c1, c1, 2`; there is no `4`. That number is important. You read *Using the Advanced SIMD and VFP in Hyp mode*; You are not using the *virtualization extensions*? Also, I don't think you need this if you are not using *TrustZone*. – artless noise Oct 07 '13 at 21:01
  • @artlessnoise can you post an answer with the full sequence ? – 0x90 Oct 07 '13 at 22:11
  • `eee8Ra10` where `R` is the register. – 0x90 Oct 08 '13 at 05:00

2 Answers2

3

A sequence for initializing the VFPU can be found in u-boot source.

.macro init_vfpu
  ldr r0, =(0xF << 20)
  mcr p15, 0, r0, c1, c0, 2
  mov r3, #0x40000000
  .long 0xeee83a10
  /* vmsr FPEXC, r3 */
.endm /* init_vfpu */

As documented in the binutils mailing list, the vmsr FPEXC bug has been fixed in the binutils 2.23 branch as well as the HEAD and the 2.24 development branch which will be released shortly. Fixes exist in the 2.23.1 and 2.23.2 releases of binutils.

Here is a sample session,

$ cat t.S
init_vpu:
  ldr r0, =(0xF << 20)
  mcr p15, 0, r0, c1, c0, 2
  mov r3, #0x40000000
  vmsr FPEXC, r3
  bx  lr
  .ltorg
$ arm-none-linux-gnueabi-as -march=armv7-a -mcpu=cortex-a15 -mfpu=neon t.S -o t.o
$ arm-none-linux-gnueabi-as --version | grep assembler
GNU assembler (crosstool-NG hg+default-86a8d1d467c8) 2.23.1
This assembler was configured for a target of `arm-none-linux-gnueabi'.
$ objdump --version | grep Binutils
GNU objdump (GNU Binutils for Ubuntu) 2.23.2
$ objdump -S t.o 

t.o:     file format elf32-littlearm

Disassembly of section .text:

00000000 <init_vpu>:
   0:   e3a0060f        mov     r0, #15728640   ; 0xf00000
   4:   ee010f50        mcr     15, 0, r0, cr1, cr0, {2}
   8:   e3a03101        mov     r3, #1073741824 ; 0x40000000
   c:   eee83a10        vmsr    fpexc, r3
  10:   e12fff1e        bx      lr

The above sequence should work for all of the Cortex-A series. The sequence is for a system without virtualization or TrustZone active.

artless noise
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2

You need to update binutils from git. This issue has been fixed earlier this year in this commit, but apparently there has been no release since then. Alternatively, encode the instruction manually.

Jester
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  • @Jake'Alquimista'LEE binutils isn't gcc. Whoever downvoted, care to explain? – Jester Oct 07 '13 at 19:32
  • @artlessnoise Ok, I'll take your word for it. The commit I found is dated later than 2.23 and I don't see 2.24 release yet (not tagged). – Jester Oct 07 '13 at 21:28
  • I see. I should have gone back more, I just found the most recent change and assumed that was the first fix. – Jester Oct 07 '13 at 21:53
  • @Jester I'm not the one who downvoted your answer. I'm upvoting it right now. You deserved this with your answer :) – Jake 'Alquimista' LEE Oct 08 '13 at 01:50