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Are x64 registers interchangable, in the sense that any instruction that works with one combination of them will work with any other? Is there performance difference or any other considerations that make them different from each other, apart from the names?

Peter Cordes
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Alexei Averchenko
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    I'm actually not sure, but looking at the [Intel manuals](http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html) will help a lot. They are a bit of a large read, but they tell you all you can/can't do with each instruction, and also give optimization suggestions. – chbaker0 Dec 28 '13 at 02:45
  • Related: [Why are x86 registers named the way they are?](https://stackoverflow.com/q/892928) – Peter Cordes Mar 20 '22 at 02:25

2 Answers2

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No. Although most x86 as well as x86_64 instructions can use any registers as GPRs, some instructions only work with a specific register or set of registers such as movabs, mul, div...

For more detailed information regarding implicit register usage read here

See also Are the data registers EAX, EBX, ECX and EDX interchangeable

phuclv
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    There are also addressing mode differences (for example there is no [rbp]. You have to fake it with [rbp+0]) and the high registers encode less compactly. – Raymond Chen Dec 28 '13 at 03:41
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    Besides that addressing with (r)bp or (r)sp uses SS as Default segment selector, while the other registers use DS. They're not necessarily equal. – PMF Dec 28 '13 at 08:03
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    @PMF: In 64-bit mode, the only difference there is that you can get a `#SS` exception instead of `#GP` if you try to deref a non-canonical address from RBP or RSP. 64-bit mode fixes the segment base for SS and DS at 0 and completely ignores SS and DS segment override prefixes. See [Why is the use of the 'DS:' segment override illegal in 64-bit mode?](//stackoverflow.com/q/50400274). But yes, that does mean that `[rbp + rdi*1 + 0]` is not exactly the same as `[rdi + rbp*1]` in every possible corner case so an assembler maybe shouldn't optimize that for you. :P – Peter Cordes Jan 23 '20 at 05:34
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There are some restrictions, and some differences in encoding.

rsp (and esp, etc) may not be used as an index register. There are many instructions which take arguments or return results in particular registers - for example, the variable shift instructions only take their argument in cl.

The arithmetic instructions (and test) have short encodings for rax plus a 32-bit immediate:

8:  48 05 ff ff 00 00       add    $0xffff,%rax
e:  48 81 c3 ff ff 00 00    add    $0xffff,%rbx

I'm sure there are some other bits and pieces I can't bring to mind at the moment: consult the architecture manual for the gory details.

gsg
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