How to see exactly what make is doing

Question

Ive got some large make files for a third party project that are not building due to linker issues.

From looking at the make files, I think it should be executing something like:

LIBS = -lm
CC = gcc
bin = bin
myapp: $(bin)/main.o $(bin)/other.o $(bin)/etc.o
    $(CC) $(bin)/main.o $(bin)/other.o $(bin)/etc.o $(LIBS) -o myapp

gcc bin/main.o bin/other.o bin/etc.o -lm -o myapp

Instead from the error it seems to be failing on something like: It also didn't put any of the .o files in the expected bin/ location, but just left them in the source directory...

cc main.o -o myapp

But I cant locate anywhere that might come from. Is there some way to get some kind of stacktrace through the make files?

I am aware of -n and -d, but neither seems to tell me what target line and file yeilded that command, or which series of targets led there and the values of any $() expansions (The one im expecting is the only myapp: I can find in any of the makefiles...)

@Graeme Thanks, I hadn't realised that. VERBOSE=1 also works for cmake generated makefiles, but perhaps under the hood cmake uses autotools? — , Jan 27 '14 at 14:30
`cmake` is an alternative and more cross platform, although it may create the same or similar variables. I don't see either in the question though! — Graeme, Jan 27 '14 at 14:36
This question is repeating this question: https://stackoverflow.com/questions/5820303/how-do-i-force-make-gcc-to-show-me-the-commands — Peter Teoh, May 22 '19 at 08:10

score 0 · Answer 1 · edited Jun 20 '20 at 09:12

0

Check out the --debug option. From my manpage:

--debug[=FLAGS]

       Print debugging information in addition to normal processing.  If the
       FLAGS are omitted, then the behavior is the same as if -d was specified.
       FLAGS may be a for all debugging output (same as using -d), b for basic
       debugging, v for more verbose basic debugging, i for showing implicit
       rules, j for details on invocation of commands, and  m  for debugging
       while remaking makefiles.

edited Jun 20 '20 at 09:12

Community

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answered Jan 27 '14 at 14:21

Graeme

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I still dont see how to find out where in the MakeFile it is? Like i said i traied -d and it outputs a load of "Looking for rule", "Trying pattern rule", "Trying implicit perquisite", and in the end just says "Must remake target 'myapp'" and issues the command I showed. How do I find out where that command comes from? I know it must have found a rule for "myapp", but where does it say where that rule is located within the filesystem? (I did try searching the entire source tree, and just found the rule in my question, but that clearly isnt what is being executed right?) – Fire Lancer Jan 27 '14 at 14:33
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@FireLancer My bad, I thought the `--debug` option would give more than `-d`. The second sentence from my man page there is actually wrong. Anyway, look at this question - http://stackoverflow.com/questions/54753/tool-for-debugging-makefiles, `remake` seems like a good idea. – Graeme Jan 27 '14 at 14:42

score 0 · Answer 2 · answered Jan 27 '14 at 16:38

remake is a very good choice but in a pinch something like the following (saved as debug.mk) can be a good help too. It won't tell you as much as remake but it might tell you enough to start with.

# Use as: MAKEFILES=debug.mk make
OLD_SHELL := $(SHELL)

ifneq (undefined,$(origin X))
override X = -x
endif

SHELL = $(if $@,$(warning Running $@$(if $<, (from: $<))$(if $?, (newer: $?))))$(OLD_SHELL) $(X)

You can print out the other automatic variables there too if you wanted to see a bit more about what was going on.

How to see exactly what make is doing

2 Answers2