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I'm implementing a hypervisor on ARM and I need to know if there's a way to resume (ERET) the guest and trap after a single instruction execution, without depending on the debug architecture (v7.1). I could use a software approach by modifying the next instruction of the guest to a HVC (equivalent of VMCALL on Intel), but I don't know how to handle instructions that cause branching (JMP).

On Intel I could use either the trap flag (=TF bit in RFLAGS, per-OS-thread-context) or the monitor trap flag (=MTF, VT-x feature).

Thank you

EDIT: Clarifications

  • I want to avoid disassembly/emulation (as much as possible)
Jolta
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Zuzu Corneliu
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    If you have a hypervisor, you should have the debug too. Why you don't want to use it? – Igor Skochinsky Feb 05 '14 at 12:36
  • Place two `HVC` instructions, one after the branch instruction and one at the branch target? – tangrs Feb 05 '14 at 12:43
  • @IgorSkochinsky because it implies complication of the hypervisor code; that is: 1. CPU must be put in debug state temporarily (performance issues?) 2. If I trap debug exceptions I'm also bound to trap CP14 reads/writes, debug ROM access, debug OS related register access so I'd have to emulate those too (performance issues here as well).. – Zuzu Corneliu Feb 05 '14 at 14:07
  • @tangrs I want to avoid disassembly/emulation of guest code – Zuzu Corneliu Feb 05 '14 at 14:09

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