Approximate latency to access caches and main memory via QPI (dual socket/processor)

Asked Mar 18 '14 at 23:13

Active Nov 29 '15 at 14:09

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This thread has a good list of times that it takes to access various parts of the computer architecture in a uniprocessor environment. How about in a dual processor environment, over Intel's QPI bus?

Let's assume a 64 byte packet memory is allocated on the first CPU. The second CPU has to access this via a 8.0 GT/s QPI bus, so I know the serialization latency alone is 4~ ns. What additional latency should I expect on the QPI bus?

edited May 23 '17 at 11:44

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asked Mar 18 '14 at 23:13

elleciel

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Did the first CPU modify the line? does it still reside in its L1/L2 caches? – Leeor Mar 18 '14 at 23:47
@Leeor Hm, I'd like to hear the latency for both cases. – elleciel Mar 19 '14 at 00:53

Approximate latency to access caches and main memory via QPI (dual socket/processor)

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