How to make lots of similar executables

Question

I have a test directory with a makefile like:

    EXECS = pgm1 pgm2 pgm3 pgm4 pgm5 ...

    OBJS = $(addsuffix .o, $(EXECS))

    all: $(EXECS)

    %.o : %.c
        $(CC) -c $< -o $@ $(IFLAGS)

    $(EXECS) : $(OBJS)
        $(CC) $@.o -o $@ $(LFLAGS)

    pgm1 : pgm1.o
        $(CC) $< -o $@ $(LFLAGS)

    % : %.o
        $(CC) $< -o $@ $(LFLAGS)

The pgm1 : pgm1.o link rule works, but I don't want to have to enter one for each program.

The % : %.o rule doesn't work (it picks up a default rule with no link flags)

The $(EXECS) : $(OBJS) rule works, but all the executables are linked every time a .o file changes. This doesn't really matter 'cos the programs are small, but it would be nice to fix.

Any suggestions, please?

Later...

Thanks to all for your suggestions. The solution is a gloriously simple combination of all of them:

% : %.c
    $(CC) $(IFLAGS) $< -o $@ $(LFLAGS)

You can try this: http://stackoverflow.com/questions/1490949/how-to-write-loop-in-makefile — user2076694, Mar 20 '14 at 14:30

score 0 · Answer 1 · answered Mar 20 '14 at 14:39

The %:%.o rule should work, but I guess that make is using a higher-priority default rule as

%:%.c
    $(CC) $@.o -o $@

that compiles and links directly from the C, without your variables.

You can redefine this default rule to suit your need, or drop it by writing

%:%.c

with no command, see http://ftp.gnu.org/old-gnu/Manuals/make-3.79.1/html_chapter/make_10.html#SEC104

score 0 · Answer 2 · answered Mar 20 '14 at 14:55

The pattern rule doesn't work because you've already defined an explicit rule for the targets, in the $(EXECS) : $(OBJS) line. Explicit rules take precedence over implicit rules, like pattern rules. Remove the explicit rules and it will work as you want:

EXECS = pgm1 pgm2 pgm3 pgm4 pgm5 ...

all: $(EXECS)

%.o : %.c
    $(CC) -c $< -o $@ $(IFLAGS)

% : %.o
    $(CC) $< -o $@ $(LFLAGS)

How to make lots of similar executables

2 Answers2