6

I am not sure, but if I remember right Intel uses a VIPT (virtual index physical tagged) cache, I would like to know the reason of this choice, why is it better than VIVT or PIPT, what advantages does it procure and maybe what disadvantages. Thank you.

johan
  • 1,664
  • 2
  • 14
  • 30
PiggyGenius
  • 443
  • 2
  • 9
  • 25

2 Answers2

6

The exact design decisions are probably not published, but in general the benefits for VIPT are :

  1. Virtual indexing means you can start reading the set from the cache before (or in parallel with) looking up the translation in the TLB. This means that the common case lookup would be done much faster than a physically indexed cache, where you can only lookup the cache after you have the translation.
  2. Physical tagging allows you to avoid aliasing - both in cases where a single virtual address maps to several physical ones (e.g. different threads overlapping in virtual addr ragne), or multiple virtual addresses map to the same physical line (e.g. inter-thread communication). Both cases may cause loss of coherency in a virtually tagged cache and would require complicated mechanisms for detection.
Jonathon Reinhart
  • 132,704
  • 33
  • 254
  • 328
Leeor
  • 19,260
  • 5
  • 56
  • 87
  • 1
    Than you for your answer, so the lost of performance with vipt, compared to vivt, is the price Intel is willing to pay to deal with one virtual address referencing multiple physical ones and multiple virtual address referencing one physical address ? Isn't there an other to deal with these problems using vivt ? – PiggyGenius Mar 21 '14 at 23:22
  • 2
    There are other ways, otherwise VIVT wouldn't have been possible, but that involves complicated matches. VIPT on the other hand doesn't necessarily lose performance - assuming TLB hits are the common case and the internal plumbing can bypass the translation fast enough for the tag match, you can get your cache lookups done just as fast as VIVT – Leeor Mar 21 '14 at 23:28
  • Thanks a lot for your time you answered perfectly at my questions. – PiggyGenius Mar 21 '14 at 23:47
  • Could you please explain how using Virtual Index and Physical Tag resolves aliasing? Isn't it possible for one physical address to have 2 corresponding virtual addresses where the index bits are the same? – Myath Apr 11 '18 at 21:08
  • @Myath: The trick is for the cache to be small and associative enough that the index bits all come from the page-offset and thus translate for free, making the cache effectively PIPT. [Why does intel use a virtual index physical tagged cache and not VIVT or PIPT?](https://stackoverflow.com/q/22570526) / [Why is the size of L1 cache smaller than that of the L2 cache in most of the processors?](https://stackoverflow.com/a/38549736). Or when that's not quite the case, OS can do page colouring: [Virtually indexed physically tagged cache Synonym](https://stackoverflow.com/q/46588219) – Peter Cordes Jul 11 '20 at 00:11
  • Oops, one of those links in my last comment was this question. I probably meant to link [Minimum associativity for a PIPT L1 cache to also be VIPT, accessing a set without translating the index to physical](https://stackoverflow.com/q/59279049) – Peter Cordes Jul 22 '23 at 19:44
-1

"vivt pipt" is a commonly used mapping scheme in computer caches. It stands for "Virtual Index, Virtual Tag, Physically Indexed Physically Tagged". In this mapping scheme, cache blocks are indexed by virtual addresses and tagged with virtual addresses, but the indexing is performed physically and the tags are stored physically.

yugang wu
  • 1
  • 1
  • my，first comments – yugang wu May 15 '23 at 03:15
  • Defining the terms VIVT and PIPT doesn't answer the question of why Intel CPUs chose VIPT. Also, you aren't defining anything correctly: "VIVT PIPT" isn't a single mapping scheme. And indexing doesn't involve the tag, that's used when selecting a way from the set selected by the index bits. – Peter Cordes May 15 '23 at 19:22