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We always talks about how to better use cache to speed up the program. However, if I have a background program, which is not latency-sensitive. I also have some latency-sensitive program running on the same computer. In order to avoid the background program pollute the cache of the latency-sensitive program, I have two choices:

1) Use page-color or some other techniques to "partition" cache and let the latency-sensitive program run in several cache colors, while background programs never uses the memory with those cache colors. <-- I know how this works and have no question on this approach.

2) Can we just mark the memory used by the background program as not-cachable? In other words, all of the memory access from the background program will by-pass the cache so that the cache won't be polluted?

I know we could bypass al of the cache on the machine by setting the 30th bit of CR3 register. But how can we just make some programs by-pass the cache while the others programs still use cache?

[ADD A QUESTION] Is it possible to mark a memory page bypass the cache? In other words, can we mark a memory page not cachable?

Thank you very much for your insight!

Mike
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    This could potentially do more harm than good, since you'll be using a lot more FSB bandwidth if you somehow prevent caching for one process, and this may then become a bottleneck for all processes. – Paul R May 08 '14 at 21:28
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    On a multi-core processor, you may be able to run the latency-sensitive program on its own core, so it has a separate cache to work with. – user3386109 May 08 '14 at 21:29
  • @PaulR, Thank you so much for pointing out the FSB issue! I agree when FSB becomes the bottleneck, the task that fetch data from memory will be affected and has longer delay. However, if all of the data of the task have been loaded into cache, the FSB should be affect the task any more. Am I correct? – Mike May 09 '14 at 02:12
  • @user3386109, I think you are talking about private cache but they can still have cache interference in shared cache. Because of the inclusive property of Intel cache, it will also affect the private cache of one core from another core. Do you have any insight on avoiding using shared cache for a task? – Mike May 09 '14 at 02:13

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You can use the Memory Type Range Registers (MTRRs) and/or Page Attribute Table (PAT) features of modern x86 processors. You can use these features to mark certain regions of memory as uncacheable. In particular, you can use the UC, UC-, or WC memory types. But you'll have to know which regions of memory are used by the latency-insensitive application. For more information, refer to the Intel manual Volume 3 Chapter 11: Memory Cache Control.

The closest thing you can do in user mode is by using non-temporal accesses (NTAs).

I know we could bypass al of the cache on the machine by setting the 30th bit of CR3 register.

I think you mean bit 30 of CR0, not CR3.

Hadi Brais
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