-4

I am trying to figure out a binary bomb lab, phase 5. This is not a homework assignment but rather something I am doing on my own.

I found a similar question answered here but I didn't understand the answer since there actual values were not plugged in. I am trying to figure out what, exactly, ends up in %al, assuming that %al is the destination. I am using gdb and the i r command showed that %ebx holds the string I entered for input, which was "device", and %edx has 0. What does this do?

Community
  • 1
  • 1
user1317750
  • 51
  • 2
  • 8
  • I'm not assembly guru, but it looks like just assigning first byte of your `device` string to `al` register – Konstantin V. Salikhov Jul 04 '14 at 07:19
  • Possible duplicate of [What is the meaning of MOV (%r11,%r12,1), %edx?](https://stackoverflow.com/questions/2883850/what-is-the-meaning-of-mov-r11-r12-1-edx) – phuclv Aug 09 '18 at 01:30

3 Answers3

4

The equivalent Intel syntax would be mov al, [edx+ebx*1]

In other words, it's loading a byte from memory at the address formed by edx + ebx*1 and placing the byte in the al register. Note that the *1 (or , 1 in AT&T syntax) is superflous; just writing [edx+ebx] ((%edx, %ebx) in AT&T syntax) would've achieved the same thing.

In your case I suppose it's reading a character from position edx in the string pointed to by ebx. It would've made more sense for the instruction to be mov (%ebx, %edx), al in that case, since you typically scale indices and not base addresses. But since the scaling factor is 1 here, it doesn't really matter.

Michael
  • 57,169
  • 9
  • 80
  • 125
  • Actually, you cannot scale the base. In terms of Intel and AMD, **the value that you can scale is the index**. The other is base, it defines the segment register in use. Of course if base and index have same the default segment register (as `edx` and `ebx` have: `ds`) and you use a scale of 1, the difference is clear only in the encoding of the instruction. But if other was `esp` or `ebp` and the other eg. `eax`, `edx`, `ecx`, `ebx`..., the order of registers would make difference not only in the encoding, but also in the result, because of different default segment registers (`ss`/`ds`). – nrz Jul 04 '14 at 08:05
  • 1
    @nrz: Sure. But I was talking about the base address in semantic terms (i.e. the string address) rather than instruction encoding. One can write either `[base + index*scaling]` or `[index + base*scaling]` (where `base` and `index` are registers), but only one of them really makes sense. – Michael Jul 04 '14 at 08:16
1

also look D(a, b, c) too. this means a + b * c + D D means offset, a means base, b means index, c means scaling. the important point in here is the scaling must be 1, 2, 4, 8 because it related to type

MangoTatsy
  • 173
  • 1
  • 13
1

the ()ed instruction is for calculating the memory address.

(a, b, c) means a + b * c. But be aware of value of c, because it must be one of 1, 2, 4, and 8. This is because of the alignment problem.

Edwin Lee
  • 36
  • 3
  • 1
    Scaled-index addressing modes don't require alignment. It's limited to powers of 2 because it's encoded as a 2-bit shift count in the machine code. `index << 0..3`. – Peter Cordes Jan 18 '19 at 01:39