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I try to vectorize a CBRNG which uses 64bit widening multiplication.

static __inline__ uint64_t mulhilo64(uint64_t a, uint64_t b, uint64_t* hip) {
    __uint128_t product = ((__uint128_t)a)*((__uint128_t)b);
    *hip = product>>64;
    return (uint64_t)product;
}

Is such a multiplication exists in a vectorized form in AVX2?

GSerg
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Yigit Demirag
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1 Answers1

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No. There's no 64 x 64 -> 128 bit arithmetic as a vector instruction. Nor is there a vector mulhi type instruction (high word result of multiply).

[V]PMULUDQ can do 32 x 32 -> 64 bit by only considering every second 32 bit unsigned element, or unsigned doubleword, as a source, and expanding each 64 bit result into two result elements combined as an unsigned quadword.

The best you can probably hope for right now is Haswell's MULX instruction, which has more flexible register use, and does not affect the flags register - eliminating some stalls.

Brett Hale
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  • Yes, `MULX` is the right thing to use (and your compiler should generate it for you if you specify that you are targeting Haswell+) – Stephen Canon Jul 04 '14 at 19:38
  • I think `mulx` is in Broadwell, not Haswell – phuclv Dec 17 '14 at 17:50
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    @LưuVĩnhPhúc, `MULX` is Haswell. You can check this in GCC using `__int128` with `-march=haswell` (or `-mbmi2`). – Z boson Mar 23 '15 at 08:00
  • yep, probably I'm wrong because I saw on many pages claiming that MULX, ADOX and ADCX will be introduced in Broadwell – phuclv Mar 23 '15 at 09:19
  • Is it possible for me to use some other multiplication methods like Karatsuba algorithm then? – Yigit Demirag Jun 25 '15 at 12:09
  • @user1979163 - have you looked at the code generated? A 64x64-bit `mul` instruction places the 128-bit result in the `rdx` (hi) and `rax` (lo) registers. Partial products are fine on SIMD, until you have to add the 'columns' and propagate the carry - then you're using SIMD horizontally, which kills any potential benefit. – Brett Hale Jun 25 '15 at 15:47