I've been reading up on memory models in an assembly book I picked up and I have a question or two. Let's say that the address bus has 32 lines, the data bus has 32 lines and the CPU is 32-bit (for simplicity). Now if the CPU makes a read request and sends the 32bit address, but only needs 8 bits, all 32 bits come back anyway? Also, the addresses in memory are still addressed per byte correct? So fetching one byte would bring back 0000 0001 to address 0000 0004?
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1Address 0000 0000 to 0000 0003, but you got it. – Potatoswatter Mar 21 '10 at 18:43
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What is the question? Behaviour `mov 0, %al` also zeroes `ah`, or performance? – Ciro Santilli OurBigBook.com Oct 30 '15 at 20:23
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1@CiroSantilli新疆棉花TRUMPBANBAD: a load from absolute address `0` into AL doesn't affect AH. (I think you know that, but your previous comment sounds misleading, like you're stating that it does, not asking just asking the OP if that's what they're asking.) – Peter Cordes Apr 15 '21 at 20:58
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You should really read this: [What Every Programmer Should Know About Memory](http://lwn.net/Articles/250967/) – Paul R Apr 16 '21 at 07:09
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In general, yes. There's nothing to be gained by reading parts of a word from a bus, so a whole word is read. Instructions specify which parts of the words they need to actually load or store in registers.
That said, it's rare to read directly from the memory these days. CPUs have caches with which you interact 99% of the time, and when data isn't in the cache, a whole line is brought in (multiple words) and then you still read from the cache.
Also note that many modern CPUs actually have 64-bit buses.
Eli Bendersky
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Any good books you can recommend in regards to cpu architecture, memory models, etc? Thanks! – IM. Mar 21 '10 at 18:31
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1@IM: the best one I know of is http://www.amazon.com/Computer-Organization-Design-Fourth-Architecture/dp/0123744938/ref=sr_1_1?ie=UTF8&s=books&qid=1269196510&sr=8-1-spell – Eli Bendersky Mar 21 '10 at 18:35
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uncacheable MMIO reads do have to signal over the bus which specific byte is being read. On CPUs with a "frontside" bus (instead of sorting out IO vs. DRAM inside the chip), you'd have byte-enable lines for each of 4 bytes in a 32-bit bus. More complex busses like x86 used up until K8 / Nehalem integrated memory controllers might do it differently for uncacheable load or store (like some kind of "message" with a header, instead of dedicated pins), IDK. – Peter Cordes Apr 15 '21 at 21:02