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See the following code from jdk8/openjdk/hotspot/src/os_cpu/linux_sparc/vm/linux_sparc.s:

_flush_reg_windows:
    ta 0x03
    retl
    mov     %fp, %o0

What does the code above mean?

I can't understand what ta means.

Also, why there exists code after retl. Nothing should exist after ret, right?

In the instruction mov %fp, %o0 what does %o0 mean? Does %fp refer to FramePointer FP register?

Plus, another small question:

mov    %eax, 0xfffffffc(%ebp)

What does 0xfffffffc here mean?

phuclv
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yangyixiaof
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  • Reffer the manual of assembly language of Sparc at http://docs.oracle.com/cd/E19641-01/802-1947/802-1947.pdf You need to know a lot about assembly language and machine language of Sparc. – Fumu 7 Sep 17 '14 at 06:59
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    _"what does '0xfffffffc' mean?"_ `0x` is a prefix used for [hexadecimal literals](http://en.wikipedia.org/wiki/Hexadecimal). – Michael Sep 17 '14 at 07:16
  • Read more about [sparc](http://en.wikipedia.org/wiki/SPARC) architecture. There's no common architecture for all CPUs – phuclv Sep 17 '14 at 10:45
  • about the second question http://stackoverflow.com/questions/8186965/what-do-numbers-using-0x-notation-mean http://stackoverflow.com/questions/2670639/why-are-hexadecimal-prefixed-as-0x – phuclv Sep 17 '14 at 10:52

1 Answers1

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As far as I understand your question correctly you are not really aware of the fact that different processor architectures (like x86, ARM, Sparc, MIPS, PowerPC) use a completely different instruction set.

For this reason assembler code (and instructions) for these processors will look absolutely different.

The first fragement of code is obviously Sparc assembly code. Sparc processors were used in larger Sun (now Oracle) workstations. The way these processors work is very different to x86 processors used in a PC.

Registers are named %o0-%o7, %g0-%g7, %l0-%l7 and %i0-%i7 on such processors. %fp is the "special name" of one of these registers (%i6 = %fp).

Just like MIPS processors such CPUs have "delay slots". This means that a Jump, Call or Return instruction will execute with one instruction delay. This means the instruction following a jump or ret instruction is executed before the actual jump takes place.

For this reason there is an instruction after the "retl" instruction!

The "ta" instruction is similar to the "int" instruction on x86 CPUs: It executes an operating system interrupt.

As "Michael" already set 0xFFFFFFFC is a hexadecimal number; in this case -4.

"mov %eax,0xfffffffc(%ebp)" is code for x86 CPUs. The instruction will load a value that is stored at the address ebp-4 into the register eax.

Martin Rosenau
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