Presented below is my makefile
# Location of the CUDA Toolkit
CUDA_PATH ?= /usr/local/cuda-6.0
NVCC := $(CUDA_PATH)/bin/nvcc -ccbin g++
APP := app
OBJ := obj
source_files = $(shell find ./src -type f -regex '.*\.\(c\|cu\|cpp\)' | sed 's/^\.\/src\///')
obj_files = $(patsubst .c,obj/.o,$(patsubst .cpp,obj/.o,$(patsubst .cu,obj/.o,$(source_files))))
vpath %.c ./src/
vpath %.cpp ./src/
vpath %.cu ./src/
# Target rules
all: exe
%.o: %.cu
-mkdir -p $(dir $@)
$(NVCC) $+ -c -o $@
exe: $(obj_files)
$(NVCC) $^ -o $(APP)
run: exe
./$(APP)
clean:
rm -f $(APP) obj/*.o
clobber: clean
I have two question:
1) How I can get makefile to work with cpp, c and cu files Now, I have
%.o: %.cu
-mkdir -p $(dir $@)
$(NVCC) $+ -c -o $@
But, I want something like that
%.o: %.cu, %.cpp, %.c
-mkdir -p $(dir $@)
$(NVCC) $+ -c -o $@
2) How I can place obj into different location. In my makefile I have variable $(OBJ) = obj and I want to put object files into this directory. How I can do this?