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Caches with Write Back Cache, perform write operations to the cache memory and return immediately. This is only when the data is already present in the cache. If the data is not present in the cache, it is first fetched from the lower memories, and then written in the cache.

I do not understand why it is important to first fetch the data from the memory, before writing it. If the data is to be written, it will become invalid anyways.

I do know the basic concept, but want to know the reason behind having to read data before writing to the address.

I have the following guess,

This is done for Cache Coherency, in a multi-processor environment. Other processors snoop on the bus to maintain Cache Coherency. The processor writing on the address needs to gain an exclusive access, and other processors must find out about this. But, does that mean, this is not required on Single-Processor computers?

Peter Cordes
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gkernel
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  • See also [Why data is fetched from main memory in Write Allocate cache policy](https://stackoverflow.com/q/64942523) - reading to get exclusive ownership before modifying is also important for MESI coherency. Also [MESI protocol. Write with cache miss. Why needs main memory value fetch?](https://stackoverflow.com/q/39180919) – Peter Cordes May 07 '22 at 09:08

2 Answers2

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Short answer

A write that miss in the cache may or may not fetch the block being written depending on the write-miss policy of the cache (fetch-on-write-miss vs. no-fetch-on-write-miss). It does not depend on the write-hit policy (write-back vs. write-through).

Explanation

In order to simplify, let us assume that we have a one-level cache hierarchy:

-----     ------     -------------
|CPU| <-> | L1 | <-> |main memory|
-----     ------     -------------

The L1 write-policy is fetch-on-write-miss.

The cache stores blocks of data. A typical L1 block is 32 bytes width, that is, it contains several words (for instance, 8 x 4-bytes words).

The transfer unit between the cache and main memory is a block, but transfers between CPU and cache can be of different sizes (1, 2, 4 or 8 bytes).

Let us assume that the CPU performs a 4-byte word write.

  1. If the block containing the word is not stored at the cache, we have a cache miss. The whole block (32 bytes) is transferred from main memory to the cache, and then the corresponding word (4 bytes) is stored in the cache.

    1. A write-back cache would tag the block as dirty (not invalid, as you stated).
    2. A write-through cache would send the updated word to main memory.

  2. If the block containing the word is stored at the cache, we have a cache hit. The corresponding word is updated.

More information: Cache Write Policies and Performance. Norman P. Jouppi.
http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-91-12.pdf

chus
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1

Your guess is almost correct. However this behavior has to be done also in multi-core single processor systems.

Your processor can have multiple cores, therefore when writing a cache line (in a WB cache), the core that issues the write needs to get exclusive access to that line. If the line intended for write is marked as dirty it will be "flushed" to the lower memories before being written with the new information.

In a multi-core CPU, each core has it's own L1 cache and there is the possibility that each core could store a copy of a shared L2 line. Therefore you need this behavior for Cache Coherency.

You should find out more by reading about MESI protocol and it's derivations.

VAndrei
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