makefile - how to exclude file extension suffix from a variable

Question

the next makefile receive the file to compile from its command line arg -ARGS. For example

make ARGS="out.c"

I would like to replace the name of the created executable "run" with the variable ARGS excluding the suffix

in this example : run="out"

all: Task1
Task1: outputs/output.o
 gcc -g -m32 -Wall -o run outputs/output.o 

outputs/output.o: outputs/${ARGS}
 gcc -m32 -g -w -Wall -ansi -c -o outputs/output.o outputs/${ARGS} 


.PHONY: clean
run: clean Task1
clean:
 rm -f outputs\output.o Task1

Your question is unclear. How exactly do you invoke `make`, and what do you want it to do? — Basile Starynkevitch, Feb 19 '15 at 21:38
Are you sure you want the object file to be named `output.o`? — Beta, Feb 19 '15 at 21:38
On which OS? If on Linux, the backslash for the `clean` target `rm` command is wrong! — Basile Starynkevitch, Feb 19 '15 at 21:41
Why does the `clean` rule attempt to remove `Task1`, a file that nothing ever builds? — Beta, Feb 19 '15 at 21:45
I'm really surprised people spend more time asking ill-formulated questions (and waiting for answers) here than reading documentation. — Basile Starynkevitch, Feb 19 '15 at 21:55
@BasileStarynkevitch: 1) Don't forget about selection bias, and 2) don't underestimate human laziness. — Beta, Feb 19 '15 at 22:24

score 3 · Accepted Answer · answered Feb 19 '15 at 21:51

The crude way to do what you ask is simply:

EXEC := $(basename $(ARGS))
all: Task1
Task1: outputs/output.o
    gcc -g -m32 -Wall -o $(EXEC) outputs/output.o

A better way is:

EXEC := $(basename $(ARGS))
all: $(EXEC)
$(EXEC): outputs/output.o
    gcc -g -m32 -Wall -o $(EXEC) outputs/output.o

Better still:

EXEC := $(basename $(ARGS))
all: $(EXEC)
$(EXEC): outputs/output.o
    gcc -g -m32 -Wall -o $@ $^

score 1 · Answer 2 · edited May 23 '17 at 12:14

1

If using GNU make you need the basename function, perhaps as $(basename $(AUX)). Maybe variables like $(*F) might be useful too (please read the documentation). However, your Makefile is probably wrong.

^{I can't suggest an improvement, because what you want to do and to happen is unclear.}

BTW, use remake (as remake -x) or at least make --trace (with a recent enough GNU make 4.x) to understand what make is doing and why.

Also, you'll find several examples of Makefile-s: here & there etc... Don't forget that make has a many builtin rules, you'll get them by running make -p

^{You won't lose your time by reading the documentation of GNU make, and some tutorials, and some examples of Makefile-s.}

edited May 23 '17 at 12:14

Community

1
1

answered Feb 19 '15 at 21:36

Basile Starynkevitch

223,805
18
296
547

hi thanks for your help. I suppose to create a makefile for compiling c with 2 requirements : 1. The makefile recieves its filename from the command line 2. The executable file created by the makefile should be with the same name without the suffix . I am open for any improvements .However, I havent seen a better way to create makefile for my requirements – this is213421 Feb 19 '15 at 21:50
2

My suggestion is to spend an hour reading the documentation and the examples. It is faster, and you'll learn more, than just waiting for answers on a forum. – Basile Starynkevitch Feb 19 '15 at 21:52

makefile - how to exclude file extension suffix from a variable

2 Answers2