Recursive make with nonstandard makefile name on old make version

Question

I have a makefile which calls itself, in order to obtain a license for the compiler before compiling anything, and release the license even when compilation fails, like this:

.PHONY main_target
main_target:
    @license_grab &
    @sleep 2
    -@$(MAKE) real_target
    @license_release

This works great if the makefile is named "makefile". But if I make a copy of the makefile to experiment with something, and invoke it with make -f makefile_copy, then the wrong makefile gets used in the recursive call. How do I prevent this without hard-coding the makefile name in the makefile itself?

Edit: Unfortunately I'm stuck using GNU Make version 3.79.1, so I cannot use MAKEFILE_LIST, which was apparently introduced in version 3.80. Therefore none of the answers in this question will work for me.

score 2 · Answer 1 · answered Mar 05 '15 at 19:47

2

You can use the MAKEFILE_LIST variable:

THIS_MAKEFILE := $(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST))

.PHONY main_target
main_target:
        @license_grab &
        @sleep 2
        -@$(MAKE) -f $(THIS_MAKEFILE) real_target
        @license_release

answered Mar 05 '15 at 19:47

MadScientist

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Thanks, that looks like a great answer for recent versions of make. Unfortunately the version I'm using is very out of date and doesn't have support for MAKEFILE_LIST; I added that info to my question. – Ben Mar 05 '15 at 20:34
Then you're out of luck. You'll have to either set a variable on the command line by hand or hardcode the file name. You can write a little shell alias or script wrapper around make that will do it for you, but there's no really reliable way to do it from within the makefile. – MadScientist Mar 05 '15 at 21:37

score 1 · Accepted Answer · edited Mar 06 '15 at 23:09

1

You can set the MAKE variable outside the makefile, to include the makefile name (unless of course, it gets overridden). Something like this (for bash):

MAKE="make -f makefile_copy" make -e -f makefile_copy

or this (in pretty much any shell):

make MAKE="make -f makefile_copy" -f makefile_copy

edited Mar 06 '15 at 23:09

Ben

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answered Mar 05 '15 at 21:48

Thomas Dickey

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Thanks! That looks like an elegant workaround. The better answer of course is to use a more recent `make` supporting MAKEFILE_LIST as in the other answer, but this should do in a pinch. – Ben Mar 05 '15 at 23:03
I use this in a few of my programs - while doing recursive makes passing the MAKE and MAKEFLAGS symbols in the recursive calls (to ensure that it those were set in the lower-levels, that they're overridden). – Thomas Dickey Mar 06 '15 at 00:25
This works great for bash, for csh I used `make MAKE="make -f makefile_copy" -f makefile_copy`. It seemed to work, but is that actually equivalent or am I missing something subtle? – Ben Mar 06 '15 at 15:32
With the "-e", it is equivalent. Passing environment variables into programs like that is just a habit I picked up, long ago. "make" has long had (checking SunOS 4...) the `variable=value` syntax. – Thomas Dickey Mar 06 '15 at 21:57

Recursive make with nonstandard makefile name on old make version

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