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Following link says that "Access to device registers is always uncached"

http://techpubs.sgi.com/library/dynaweb_docs/hdwr/SGI_Developer/books/DevDrvrO2_PG/sgi_html/ch01.html

My Question is do we ever need volatile when access to device registers which is memory mapped?

Amit Singh Tomar
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2 Answers2

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The confusion here comes from two mechanisms which have similarities in their goals, but quite distinct mechanisms and levels of implementation.

The link refers to memory mapped I/O regions being configured as ineligible for hardware caching in fast intermediate memory that is used to speed operations compared to accessing slower main memory banks. This is traditionally nearly transparent to software (exceptions being things like modifying code on a machine with distinct instruction and data caches).

In contrast, volatile is used to prohibit an optimizing compiler from performing "software" caching of values by strategically holding them in registers, delaying calculating them until needed, or perhaps never calculating them if un-needed. The basic effect is to inform the compiler that the value may be produced or consumed by a mechanism invisible to its analysis - be that either hardware beyond the present processor core, or a distinct thread or context of execution.

Chris Stratton
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  • Ok, but lets assume a system where I don't have any level of cache and even if compiler optimize a variable(say Status register) ,isn't it variable read is force from memory bank(Always latest status is read). – Amit Singh Tomar Mar 17 '15 at 15:34
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    Unless you use the `volatile` keyword, the compiler can assume that the "memory location" (actually a memory mapped status register, but it has no way of knowing that) will never change unless the compiler itself changes it, so it is free to read the value once and cache it in a register. That would probably not give the operation you desire, which is why you need volatile. This is entirely distinct from what the link was talking about. – Chris Stratton Mar 17 '15 at 15:36
  • Ok,so what you are saying is if we don't use volatile keyword, compiler in its optimization operation can put/cached frequently used variable(Status register) into CPU register(not in l1/l2 cache) for faster access and never would access actual memory mapped Status register even if value of status register got changed? – Amit Singh Tomar Mar 17 '15 at 15:48
  • Yes. But the compiler doesn't know anything about l1/l2 cache - that is automatically and dynamically controlled at runtime, unless you insert one of the cache control instructions (such as flushing an instruction cache when you have modified that memory as data) – Chris Stratton Mar 17 '15 at 15:50
  • Ok but when and how(On what basis) compiler decides this particular variable has to be optimized , is it like at compile time it self compiler say this variable is optimized and at run time directly load this variable in to CPU registers(Never loaded into RAM)? – Amit Singh Tomar Mar 17 '15 at 15:59
  • The compiler makes strategic decisions at compiler time as to what it thinks will be most efficient. This is going far, far beyond the bounds of an SO question - you really want to do some reading in primary resources. – Chris Stratton Mar 17 '15 at 16:03
  • Oh sorry, I just took the discussion too far but any ways Thanks for your kind inputs, it helped :) – Amit Singh Tomar Mar 17 '15 at 16:07
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This question is a more procesor-specific version of Why is volatile needed in C?

This is one of the two situations where volatile is mandatory (and it would be nice if compilers could know that).

Any memory location which can change either without your code initiating it (I.e. a memory mapped device register) or without your thread initiating it (i.e. it is changed by another thread or by an interrupt handler) absolutely must be declared as volatile to prevent the compiler optimizing away memory-fetch operations.

Community
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kdopen
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  • Your answer is incomplete, as it only focuses on the fetch aspect. There's a complimentary requirement for store. – sawdust Mar 17 '15 at 18:58
  • True, but doesn't usually bite you as often as read. The worst ones are those registers which read back differently than they write. – kdopen Mar 17 '15 at 20:55