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I'm working with this ADC: AD7903 - http://www.analog.com/media/en/technical-documentation/data-sheets/AD7903.pdf

I don't understand the limitation of the acquisition time in relation with the maximum clock speed possible for the SPI interface.

The VIO I'm using is 3.3V to have a theoretical maximum frequency of 83.33MHz (12ns min period). Let's say I use 80MHz = 12.5ns period in 3-wire driving without busy indicator.

With reference to the timing table (page 5) and the timing diagram (page 18):

  • 12.5ns x 16 clock cycles = 200ns
  • 10ns of tEN

Even with VIO = 2.5V: 15ns x 16 + 15ns = 255 ns

Why is the minimum acquisition time 290ns?

10 Rep
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FlyerDragon
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1 Answers1

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The maximum transient response listed on page 3 is 290ns for full-scale step. Therefore, to ensure minimum distortion the acquisition time must be 290ns or greater (so that all changes all the way up to a full-scale change in the acq time will be captured correctly.)

Unless you can guarantee to keep the maximum swing less than full-scale, but that's not a good way to run, and there's no way to tell the correlation between reduced swing and decreased acquisition time.

user3443369
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  • So running at maximum speed is kinda pointless right? Anything slower than 290/16 = 18.15ns so more or less 50-55Mhz should in theory respect the constraint. So in this example 40Mhz seems a good bet if I don't mind the reduction in sampling speed? – FlyerDragon Apr 02 '15 at 15:55
  • Are you talking about the SPI speed? Just FYI that can be decoupled from the conversion rate: Put the conversion clock onto CNV1 or CNV2. – user3443369 Apr 02 '15 at 17:49