What does CC?= in a Makefile mean?

Question

I have a Makefile for a C program that has the declaration

CC?=gcc

Changing it to

CC?=g++

does NOT make it compile with g++. Changing it to

CC=g++

DOES make it use g++.

So I wonder what the ?= operator does? My guess is that it looks at a environment variable to decide which compiler to use and if it's not set then use gcc? Anyone who can clear this up?

Answer 1

From http://www.gnu.org/software/make/manual/make.html:

There is another assignment operator for variables, `?='. This is called a conditional variable assignment operator, because it only has an effect if the variable is not yet defined. This statement:

 FOO ?= bar

is exactly equivalent to this (see The origin Function):

 ifeq ($(origin FOO), undefined)
   FOO = bar
 endif

Probably CC is already defined as gcc, so CC ?= g++ won't override the existing gcc.

Answer 2

The ?= operator sets the variable only if it isn't already set: info make → * Using Variables → * Setting.

Answer 3

As others mentioned, it is likely already predefined.

On GNU, you can see what is defined with make -p from a directory that does not contain a Makefile.

This is documented at: https://www.gnu.org/software/make/manual/html_node/Implicit-Variables.html

CC

Program for compiling C programs; default ‘cc’.

Usually, CC=cc by default. Then on Ubuntu 14.04 for e.g., cc is usually a symlink to gcc.

To disable all variables at once see: Disable make builtin rules and variables from inside the make file Seems currently impossible.

Answer 4

The "?" operator means set if not already set.

So, if CC is already blank CC?= will set it. If CC already contains something, it won't.

Source: http://unix.derkeiler.com/Mailing-Lists/FreeBSD/questions/2007-03/msg02057.html