Forward command-line arguments to Makefile

Question

I have a Makefile wrapping around mocha which can be called by npm test. There are several targets in the Makefile, which looks something like:

COMPILERS = --compilers coffee:coffee-script/register
REPORTER = --reporter dot
TEST_DIR = test
SRC = -name test_*.coffee
RUNNER = ${TEST_DIR}/runner.coffee
MOCHA = NODE_ENV=test ./node_modules/mocha/bin/mocha ${COMPILERS} ${REPORTER} ${RUNNER} ${TEST_DIR}

all:
    $(MOCHA) $(shell find ${TEST_DIR} ${SRC})

subtest1:
    $(MOCHA) $(shell find ${TEST_DIR}/subtest1 ${SRC})

...

Now, this is being called from package.json as npm test where npm test subtest1 runs only subtest1. However, it would be very nice to allow appending arbitrary mocha flags, so something like:

make subtest1 -g "some test I want to run"

This can be done by defining an ARGS variable, so typing:

make subtest1 ARGS="-g 'some test I want to run'"

but that's quite verbose.

Therefore, passing arguments through to Mocha would be really nice.

The closest I've come is defining ARGS at the top of the Makefile:

ARGS = $(filter-out all subtest1, $(MAKECMDGOALS))

and appending ARGS to the MOCHA variable. This can then be called as make subtest1 -- -g "some test I want to run". That works, it runs the test, but make then stops with make: *** No rule to make target-g'. Stop.`

That same error message is then presented when doing just make -- -g "some test I want to run".

So, is there any way to continue down this ARGS path and somehow suppress make from attempting to run any targets found in ARGS, and therefore allowing both all to run, and that error message to not appear? Or should I change tack completely and there's some other way of doing this?

possible duplicate of [How to pass argument to Makefile from command line?](http://stackoverflow.com/questions/6273608/how-to-pass-argument-to-makefile-from-command-line) — Louis, May 01 '15 at 16:11
It's not quite a duplicate - that question doesn't have multiple targets and doesn't work with them (at least as far as I can discern). — cazgp, May 02 '15 at 08:56

score 0 · Answer 1 · answered May 01 '15 at 13:40

You might be able to get away with that simply by adding a dummy rule for each argument, like this:

$(ARGS):

However you should not be reading your arguments from MAKECMDGOALS, it will cause all sorts of problems.

You could instead use a script or define aliases in your shell. Here's a rule that can help do that:

shortcut-%:
    @echo '$* () { make -C "$(CURDIR)" -f $(abspath $(firstword $(MAKEFILE_LIST))) $* ARGS="$$(printf "%q " "$$@")"; }'

Use it like this:

eval `make shortcut-subtest1`
subtest1 -g test

Forward command-line arguments to Makefile

1 Answers1