reconfiguring a Makefile

Question

I'm a little new to this and am trying to build a rather large project. In particular, the source code is executing the lines

gcc -Wall -W   -c -o setitimer-helper.o setitimer-helper.c
gcc -lm  setitimer-helper.o   -o setitimer-helper

This creates a linker error because according to this C: Undefined reference to floor -lm now must come after the object files.

I need to know where in the source code I can find and rearrange this. I think it's in here, but I'm unfamiliar with Unix.

CC = gcc
CFLAGS = -Wall -W
LDFLAGS = -lm

all: setitimer-helper squish-pty squish-unix

%.o: %.c
    $(CC) -c $< -o $@

%: %.c
    $(CC) $(CFLAGS) $< $(LDFLAGS) -o $@

clean:
    rm -f *.o setitimer-helper squish-pty squish-unix

Am I correct? If so, how can I fix this. If not, where should I look?

Thanks.

Try ` $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS)`. Your `%.o: %.c` rule will never be used, as make can create the binary from the c file with your other rule. — Paul Rooney, May 31 '15 at 23:18
You should be aiming for your build to look like. `gcc setitimer-helper.c -o setitimer-helper -lm`. — Paul Rooney, May 31 '15 at 23:20
@PaulRooney right, I ran that command manually to confirm it works before posting on here that it was the intended goal. — Dylan_Larkin, May 31 '15 at 23:23
Also you could just delete both rules and allow the default rules to handle it. — Paul Rooney, May 31 '15 at 23:34
The first try worked. I don't want to mess with it anymore. Appreciate the help! — Dylan_Larkin, May 31 '15 at 23:35

score 0 · Answer 1 · answered Jun 01 '15 at 02:38

0

Change the rule to build your binary to put $(LDFLAGS) at the end.

%: %.c
    $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS)

When executed the gcc command should look like.

gcc -Wall -W setitimer-helper.c -o setitimer-helper -lm

answered Jun 01 '15 at 02:38

Paul Rooney

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reconfiguring a Makefile

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