I have some problem with a makefile. I just want to test if the compilation on src/launcher.c failed or not. But before that, i just can't convert this bash code:
out=$(gcc -c src/launcher.c -o /obj/launcher.o 2>&1)
To "Makefile code"
in fact, i want to make something like that : Handling gcc warnings and output in a Bash Script but in a makefile
Please, if you have some ideas.
CC = clang
RM = rm -f
NAME = automakefile
CFLAGS += -Wall -Wextra
CFLAGS += -O2 -march=native -fomit-frame-pointer
LDFLAGS +=
OBJS_DIR = ./obj/
SRCS_DIR = ./src/
INCLUDES += -I ./src/include
OBJS_FILES = launcher.o
OBJS = $(foreach obj,$(OBJS_FILES),$(OBJS_DIR)$(obj))
all: script $(NAME)
script:
@if [ ! -d "$(OBJS_DIR)" ]; then \
mkdir $(OBJS_DIR); \
fi
$(NAME): $(OBJS)
$(CC) $(CFLAGS) $(OBJS) -o $(NAME) $(LDFLAGS)
$(OBJS_DIR)%.o: $(SRCS_DIR)%.c
//This line isn't working!
$(eval TMP=$$(gcc -c src/launcher.c -o obj/launcher.o 2>&1))
echo $(TMP)
clean:
$(RM) $(OBJS)
fclean: clean
$(RM) $(NAME)
re: fclean all
.Phony: all script clean fclean re
Thanks Have a nice day