1

How do hardware breakpoints work on ARM processors? I can see that on x86 and x64 there are 6 DEBUG registers, DR0 throught DR7. Can someone point me to resources similar to this but for ARM?

  • which architecture/core, no need to expect that from one architecture to another they behave the same. you have read the arm documentation yes? – old_timer Jun 23 '15 at 18:08
  • 1
    In ARMv6 and later there is at least a standardised debug architecture, as documented in the relevant [Architecture Reference Manual](http://infocenter.arm.com/help/topic/com.arm.doc.subset.architecture.reference/index.html#reference), but the specific details (like number of registers) still depend on what a particular core actually implements; [example picked at random](http://infocenter.arm.com/help/topic/com.arm.doc.ddi0388g/Babdifja.html). – Notlikethat Jun 23 '15 at 19:41

1 Answers1

3

ARM architectures support both Hardware and Software breakpoints. In Cortex A7 (an ARM v7a implementation from ARM) six hardware breakpoints are available. Checkout section: 10.2.2 (Breakpoints and Watchpoints) of the Cortext A7 TRM

When you run out of hardware breakpoints, there is a BKPT instruction which the debugger inserts to halt execution.

You will have to refer to the Technical Reference Manual (TRM) of the particular chip you are looking at for the exact number of hardware breakpoints.

Arun Valiaparambil
  • 545
  • 3
  • 7