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i wanted to know how to solve these problems??

An 8kb direct mapped write-back cache is organised as multiple block, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following. 1 valid bit 1 modified bit as many bits as minimum needed to identify the memory block mapped in cache. What is the total size of memory needed at the cache controller to store metadate for the cache?

please guys help me with this problem,thanks in advance

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1 Answers1

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i wanted to know how to solve these problems??

Of course this kind of question is also valid with different block sizes, different associativity, address sizes.

You can solve such questions by learning the concepts of CPU architectures. The most relevant information is here: https://en.wikipedia.org/wiki/CPU_cache

Also a dup of: Understanding CPU cache and cache line

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cruftex
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