Can someone explain this diagram on Paging (virtual memory) to me?

Question

I've been trying to understand virtual memory but when I get into the real specifics of it I just get confused. I understand (or feel like I do) the fact that virtual memory is a way for a process to "think" that it has a certain amount of memory allocated to it. The virtual address space is partitioned into equal sized pages, the physical memory is partitioned into equal sized frames, and the pages map to the frames.

But like..when does this happen? In this diagram, the CPU is running Program P. That means that a part of P was already in the physical memory, correct? (Since the cpu only has access to the physical/main memory). So what exactly is being pointed at by the CPU? I see that it's a page in the virtual memory space, so like..what exactly does this page represent? Is it an instruction? Are we moving an instruction from virtual memory to physical memory, so that more of the program is in physical memory (that hadn't been needed up until that point)? Am I way off? Can someone explain this to me?

Answer 1

The diagram shows the process of translating a virtual address to a physical address.

The fat arrow from Program P to CPU symbolizes the program being "fed" into the CPU.¹

The CPU "points" to a virtual address used by an instruction to address a memory location in the program P. It is divided into two parts:

• Page Table Index (p): the virtual address contains an index into the page table, which maps a page to a page frame (f). For a description of the mechanism, including multi-level paging, read this.
• Offset (o): as you can see, the offset is directly added to the physical address, since paging's smallest addressable unit is a page, not a byte

Finally, the calculated address is used to address a memory location in physical memory.

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¹ "fed" means "read (pronounced like red) from secondary storage into RAM and executing the program instruction by instruction".

Answer 2

I would not bother trying to understand that diagram because it makes no sense.

It is titled "Paging" but the diagram does not show paging at all.

What you are missing is that there are two steps. First there is logical memory translation (what the diagram kinda, sorta) shows.

Physical memory is arranged in an array of PAGE FRAMES of some fixed size (e.g., 1K, 4K).

Each process has a LOGICAL ADDRESS SPACE consisting of PAGES that match the page frame size.

The logical address space is defined by a PAGE TABLE managed by the operating system. The page table maps logical pages to physical page frames.

If there are two processes (X and Y), logical address Q in process X and address Y map to different physical page frames in most cases.

Usually there is a range of logical addresses that are assigned to the SYSTEM ADDRESS SPACE. Those logical pages map to the same physical page for all processes.

Processes only address logical pages. The have no knowledge of physical pages. The Program Counter register always refers to logical addresses. The CPU automatically translates logical pages to physical page frames. The translation is entirely transparent to the process. The operating system is the only thing that has any knowledge of physical page frame but it only manages the page tables; the CPU does the translation.

Paging is something different but related.

When a program accesses a memory address, the CPU attempts to translate that into a physical address within a page frame. Several steps occur.

1. The CPU locates the page table entry for the requested page. There may not be a page page table entry at all for the page. The diagram shows a contiguous logical to physical mapping. That rarely occurs. The logical address space usually has clusters of valid pages with gaps between them. If there is no page table entry for the address, the CPU triggers an exception.

2. The CPU reads the page table entry to determine if it references a valid page frame. There may be an entry for the page that has not been mapped to the logical address space (e.g., the first page is usually not mapped to trap null pointer errors). If the page has not been mapped, that triggers an exception.

3. The CPU checks whether the access is permitted for the current processor mode. Read/Write/Execute protection can be set for a page and access can be restricted by mode (kernel mode, user mode, or some other mode in some processors). If the access is not permitted, the CPU triggers an exception.

4. [Here is where paging comes in] The CPU checks whether the page has been mapped to a physical page frame. If not, the CPU triggers a PAGE FAULT. The OS responds by locating where the page is stored in a paging file, mapping the page table to a physical page frame, loading the data from the page file into memory, and then restarting the instruction.

Answer 3

I guess most of your confusion comes from the fact that the above diagram is a little bit misguided.

Please note that the lack of the IP register and some extra text @ both 'Tables' are the problematic ones. The rest is OK.

I show you below the same but fixed diagram which makes more sense.

As others guys already told you, the above diagram is just the translation scheme for the addresses that the CPU use to fetch the actual instructions & operands from P's virtual address space. Did you see it? It's all about addresses and nothing else!!!

It shows you how virtual addresses are managed by the CPU (in a paged scheme) in order to reach the next instruction or operand from the real physical memory using physical addresses.

The explanation of 'Downvoter' is great for that, so no need to add anything else.