how to make a makefile from object fiiles

Question

I'm trying to figure out how to create a makefile that will create object files and then compile them into an executable but when I try to make an object file that uses a variable that was declared in another file it won't compile to an object file. In other words if I have main.c that has a global variable var and I have another file called other.c which uses var but doesn't declare it like main.c did. Is there a way to compile them both to object files and link them so other.c sees the declaration of var in main.c? I was under the impression there was but I can't figure it out because when I do gcc -c other.c I get an error about var. (I know you can make var extern to fix this issue but I need to able to do this without doing that)

Here's the error messages I get.

   foundations.c: In function ‘FoundationC’:
   foundations.c:2:2: error: ‘DAYS’ undeclared (first use in this function)
  DAYS=DAYS+10;
  ^
  foundations.c:2:2: note: each undeclared identifier is reported only once  for each function it appears in
foundations.c:3:2: warning: incompatible implicit declaration of built-in function ‘printf’ [enabled by default]
  printf("The FoundationC Contractor completed the project - DAY %d\n",DAYS );fflush(stdout);
  ^
foundations.c:3:85: error: ‘stdout’ undeclared (first use in this function)
  printf("The FoundationC Contractor completed the project - DAY %d\n",DAYS );fflush(stdout);

So DAYS is a variable that was declared in main.c not foundations.c

EDIT: Solved I added the needed stl header file and global variable to the other file and then it was able to compile as an object file. Sorry about this question. I made it thinking that object file linking had the ability which would make that unnecessary but I guess not.

Answer 1

...but when I try to make an object file that uses a variable that was declared in another file it won't compile to an object file.

This has nothing to do with a makefile. Commands in the makefile will for example start the compiler on a .c file to produce an object file. Either this compilation succeeds, or it does not in which case the compiler gives you one or more error messages.

The problem you describe of a variable declared in another .c file will NOT halt the compiler; it will just compile the .c file and will at most give warning messages that a variable is not declared. But it will produce an object file.

At link time, the linker must be given all object files so produced (a command in the makefile starts the linker with the list of names on the command line) and then will produce an executable. If now the variable cannot be found in the object files, the link process will fail and no executable is produced. But all object files will have been produced (if there aren't errors in the compilation step).

Maybe his helps to re-formulate your question.