Why can I not include this file correctly using a makefile?

Question

My directory structure looks like this:

root
  |____SG
  |     |
  |     |____Makefile
  |     |____simple_client_main.cpp
  |
  |___EEE
        |___my_utils.h

SG is essentially my base of operations for building "simple_client", and I'm running make from here. In simple_client_main.cpp I have the following #includes:

#include <iostream>
#include <string>

#include "my_utils.h"

So I need my makefile to know where my_utils.h is. With this in mind, I want to add the root/EEE directory as an include directory. (From where I am, that would be ../EEE.)

Following the advice suggested here, my makefile looks like this:

DIR1 = ../EEE

CXXFLAGS = $(FLAG)

OBJS = simple_client_main.o
SRCS = simple_client_main.cpp

all: simple_client

simple_client: $(OBJS)
        g++ -o simple_client -I$(DIR1) $(OBJS) -lz

# [...]

depend:
        makedepend -- $(CFLAGS) -- $(SRCS)

But it doesn't work:

simple_client_main.cpp:6:25: fatal error: my_utils.h: No such file or directory 
compilation terminated.

Note that if I manually set the #include directive in the cpp as follows:

#include "../EEE/my_utils.h"

...everything works as expected.

What am I likely to be doing wrong here?

Answer 1

You need to add -I$(DIR1) to either CFLAGS or CXXFLAGS (or perhaps both), so that when the object file is compiled, the option is present in the compiler command line.

You want make to execute something similar to:

g++ -c -I../EEE simple_client_main.cpp

It should do that if you add -I../EEE to $(CXXFLAGS) or $(CFLAGS). You need to know the rules used by the make program you're using — they can vary.

When linking object files, it is too late for the -I option to be of relevance (but you should still include $(CFLAGS) or $(CXXFLAGS) in the linker command line as other options, notably -g, are of relevance when linking as well as when compiling to object code).

Here is some simple modifications to the outline makefile shown in the question.

DIR1     = ../EEE
IFLAGS   = -I$(DIR1)
CXXFLAGS = $(FLAG) $(IFLAGS)
CFLAGS   = $(IFLAGS)
LDFLAGS  =
LDLIBS   = -lz
CXX      = g++

OBJS = simple_client_main.o
SRCS = simple_client_main.cpp

all: simple_client

simple_client: $(OBJS)
        $(CXX) -o $@ $(CXXFLAGS) $(OBJS) $(LDFLAGS) $(LDLIBS)

A makefile like this stands a modest chance of working correctly. It is not clear what you might put in the FLAG macro, so I've left it. (I use UFLAGS and UXXFLAGS for 'user-defined C (or C++) flags'; they can be set on the command line and are never set by the makefile and are included in the CFLAGS or CXXFLAGS — you may be after something similar.)

Note how the linking line is almost all macros. This is normal and desirable; macros can be changed when running make without editing the makefile, but constant text cannot be changed without editing the makefile. The -c and -o options to the C and C++ compilers are about all that should ever appear as plain text.

If there are still problems, look at the built-in rule for compiling C++ source code to an object file, and tweak definitions accordingly. (You can use make -p to print the rules — you may need that to find out what is going on, but I hope not for your sake because they tend to be complex. Using make -f /dev/null -p shows the built-in rules only; that can be useful, too.)

Note that the make depend rule may need some surgery. It uses $(CFLAGS). If $(CXXFLAGS) contains extra options that are needed by the makedepend command, then you may need that instead, or even as well. If you have only C++ source, you probably only need the $(CXXFLAGS) macro in the command line.

Answer 2

Is the error coming from the compile stage, or the makedepend stage?

Because what I see above is that makedepend uses $(CFLAGS), and you haven't put -I$(DIR1) into CFLAGS.