I am learning to write makefile recently. All the documents I am reading tell me that I have to write a rule to execute commands. But I found that the following Makefile could generate object files with out any compile command. Why?
SOURCES=$(wildcard src/*.c)
OBJECTS=$(patsubst %.c, %.o, $(SOURCES))
all: $(OBJECTS)
When I type make in terminal, I get this:
cc -c -o xxx.o xxx.c
How does it happened?