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Im interested to load int atomically, I read the NDK doc and found that this __atomic_swap operation is an atomic storing operation, but didn't found an atomic load operation. Im using ARMv7 processor to run my application and writing in c. Is there any atomic store operation that I can use? Thanks!

VitalyD
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  • 32-bit loads are always atomic on ARM (i.e. no word-slicing). What behavior are you looking for? cf. http://developer.android.com/training/articles/smp.html – fadden Feb 02 '16 at 16:47
  • Thanks for the answer, so you saying that if I what to load atomically 32-bit , for example lets say "int a, b; a=4 ; b=a;" , and for me important that a will be stored in b atomically ,all I need is to ensure that the "a" and "b" are 32-bit aligned? – VitalyD Feb 03 '16 at 08:08
  • A load would be something like `ldr r0,[r1]`. `b=a;` could involve both a load and a store. – Michael Feb 03 '16 at 10:27
  • You can make it a [compiler memory barrier](https://en.wikipedia.org/wiki/Memory_ordering#Compiler_memory_barrier) with `asm volatile("ldr r0,[r1]" ::: "memory");` using gcc. See: [Cache flush from user mode](http://stackoverflow.com/questions/6046716/how-clear-and-invalidate-arm-v7-processor-cache-from-user-mode-on-linux-2-6-35) as well; atomic can have several meanings. – artless noise Feb 03 '16 at 14:12
  • @VitalyD: the SMP article I linked explains the topic in detail. The individual loads and stores will be atomic -- if one thread writes 0 and the other thread writes 32767, you will see either 0 or 32767 -- but the set of operations is not. The stores to 'a' and 'b' could be observed out of order by a different thread, and another thread could modify 'a' between the two assignments. – fadden Feb 03 '16 at 16:58
  • @fadden: Thanks! You helped me a lot! – VitalyD Feb 03 '16 at 17:54

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