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I am trying to disable hardware prefetching in my system with Atom processors(N270).

I am following the method as per the link How do I programatically disable hardware prefetching in core2duo ?

I am able to execute, 

./rdmsr 0x1a0  
366b52488

however, this gives error message

./wrmsr -p0 0x1a0 0x366d52688
wrmsr: Cpu 0 can't set MSR from 0x1a0 to 0x366d52688

Although I am able to set bit-0 and bit-3, no other bits are allowed to modify . 

./wrmsr -p0 0x1a0 0x366b52489

As per this link disable prefetcher in i3/i7 hardware prefetcher in Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, and Broadwell can be disabled via MSR at 0x1a4 address .

In Atom processor, reading at 0x1a4 is not permitted.

./rdmsr 0x1a4

rdmsr: Cpu 0 can't read MSR from 0x000001a4

I am wondering how is it possible that there is no information available related to how to disable hardware prefetcher in Atom processor, although Atom N270 and Core2duo processor are released at the same year (year 2008) and how to disable hardware prefetcher in Core2Duo is disclosed by Intel.

Any link to document to how can I disable prefetcher in Atom processors would be a great help? thank you in advance.

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bholanath
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1 Answers1

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The only reliable source to find information like this is the Intel Architecture Software Developer's Manual. There is an entire chapter dedicated to MSR (In the most recent release it's Chapter 35).

  1. The 0x1a4 or 0x1a0 MSR address that you found is machine dependent (that's why it's called Model Specific Register), meaning they might be only available on some models, or maybe removed in future models.
  2. If you go the chapter "MSRS IN THE 45 NM AND 32 NM INTEL® ATOMTM PROCESSOR FAMILY", which matches what your Atom N270. You won't be able to find any MSR related to prefetcher setting. So it means in official Intel CPU release it's not available (though in some engineering sample it might be found).
  3. There might be two reasons why it's not available, either it's not highly required feature thus removing it could save some silicon gates; or it's might be because Intel thinks this feature is best left default and not configurable to the public (subject to misuse by vendor or user and lead to poor performance in certain condition).

BTW, information about 0x1a4 MSR address could be found in IA SDM Chapter 35.5 and 0x1a0 in Chapter 35.2

Wei Shen
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  • thank you for your comment. I am trying to do an experiment to compare performance with and without presence of prefetching in different cpu architecture. So I am just praying and trying my best to find someway to disable prefetcher. – bholanath Apr 21 '16 at 20:26
  • thank you for your comment. I am trying to do an experiment to compare performance with and without presence of prefetching in different cpu architecture. So I am just praying and trying my best to find someway to disable prefetcher in my ATOM processor. I have tried to install likwid tool where it mentioned it support ATOM processor, however I am not able to install likwid in ATOM due to some error in Assembling gcc/stream_sse.so - to many operands for xor,add,cmp,mov etc – bholanath Apr 21 '16 at 20:42
  • I see. Completely understand that you want to play with those knobs. I took a look at the tool you mentioned. If you search for prefetch you would find a handful of places where it occurred. From what I see, on Atom processors it only supports reading prefetcher events. It's supported on Nehalem and after though. – Wei Shen Apr 21 '16 at 22:35
  • https://github.com/RRZE-HPC/likwid/search?utf8=✓&q=prefetch you can find all places involved with prefetch stuff and it seems like Atom prefetcher on/off support is not there. – Wei Shen Apr 22 '16 at 05:48