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While reading the Intel 64 and IA-32 Architectures Software Developer’s Manual, the operation section for the LEA instruction (load effective address) uses a calculation called EffectiveAddress(SRC) which is not defined anywhere else.

What is the definition of effective address and what does EffectiveAddress(SRC) do?

Peter Cordes
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Doug Richardson
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2 Answers2

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Section 3.7.5 (Specifying an Offset) of the same document states:

The offset part of a memory address can be specified directly as a static value (called a displacement) or through an address computation made up of one or more of the following components:

  • Displacement — An 8-, 16-, or 32-bit value.
  • Base — The value in a general-purpose register.
  • Index — The value in a general-purpose register.
  • Scale factor — A value of 2, 4, or 8 that is multiplied by the index value.

The offset which results from adding these components is called an effective address. Each of these components can have either a positive or negative (2s complement) value, with the exception of the scaling factor.

EffectiveAddress calculates an effective address using:

Base + (Index*Scale) + Displacement
Doug Richardson
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    See also [x86 addressing modes](http://stackoverflow.com/questions/34058101/referencing-the-contents-of-a-memory-location-x86-addressing-modes/34058400#34058400). They're all subsets of `base + index*scale + disp`, except for RIP-relative addressing in 64bit mode. – Peter Cordes Apr 19 '16 at 17:44
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Effective address it is offset from segment base address. When you see something like call 0x80000000 in protected mode (32-bit mode) CPU adds 0x80000000 to base address of segment pointed by CS segment register.

In 64-bit mode it equals to linear address because segmentation basically disabled.

Yevhen Grushko
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  • `call 0x80000000` is a weird example, because x86 doesn't have an absolute direct form of a near [call instruction](https://www.felixcloutier.com/x86/call), only `call rel32`. Do you mean a call from some address that results in EIP=0x80000000? Some assemblers would assemble it that way, but it's an unusual example. Also a trickier example because fetch from the new CS:EIP doesn't happen until after the `call` instruction finishes, when the next code-fetch happens, unlike with a data load/store. – Peter Cordes Feb 18 '22 at 21:46